Change in coreboot[master]: nb/intel/sandybridge/raminit_mrc.c: Use DDR3_SPD_SODIMM macro

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61399 )

Change subject: nb/intel/sandybridge/raminit_mrc.c: Use DDR3_SPD_SODIMM macro
......................................................................

nb/intel/sandybridge/raminit_mrc.c: Use DDR3_SPD_SODIMM macro

Change-Id: Ibbb6e6d44b1415b18aa59310f4d36d61b9a2a080
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/sandybridge/raminit_mrc.c
1 file changed, 3 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/61399/1

diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 0a7d192..4027708 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -14,6 +14,7 @@
 #include <device/pci_def.h>
 #include <lib.h>
 #include <mrc_cache.h>
+#include <spd.h>
 #include <smbios.h>
 #include <stddef.h>
 #include <stdint.h>
@@ -429,7 +430,7 @@
    		dimm->mod_id =					/* bytes 117/118 */
    			(pei_data->spd_data[0][118] << 8) |
    			(pei_data->spd_data[0][117] & 0xFF);
-			dimm->mod_type = 3;				/* SPD_SODIMM */
+			dimm->mod_type = DDR3_SPD_SODIMM;
    		dimm->bus_width = MEMORY_BUS_WIDTH_64;
    		dimm_cnt++;
    	}
@@ -453,7 +454,7 @@
    		dimm->mod_id =					/* bytes 117/118 */
    			(pei_data->spd_data[0][118] << 8) |
    			(pei_data->spd_data[0][117] & 0xFF);
-			dimm->mod_type = 3;				/* SPD_SODIMM */
+			dimm->mod_type = DDR3_SPD_SODIMM;
    		dimm->bus_width = MEMORY_BUS_WIDTH_64;
    		dimm_cnt++;
    	}