Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46359 )
Change subject: soc/intel/broadwell/romstage/pch.c: Drop reg-script usage ......................................................................
soc/intel/broadwell/romstage/pch.c: Drop reg-script usage
Change-Id: I0e83eb724edc41514928482afe1bc90fb782e852 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/romstage/pch.c 1 file changed, 21 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/46359/1
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index 9afb4e4..d68e17e 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -4,7 +4,6 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/smbus_host.h> -#include <reg_script.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pch.h> @@ -15,7 +14,8 @@ #include <soc/smbus.h> #include <soc/intel/broadwell/chip.h>
-const struct reg_script pch_interrupt_init_script[] = { +static void pch_route_interrupts(void) +{ /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP PCIE INTA -> PIRQA @@ -28,38 +28,26 @@ */
/* Device interrupt pin register (board specific) */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IP, - (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IP, (INTA << D29IP_E1P)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IP, - (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IP, (INTA << D27IP_ZIP)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D26IP, (INTA << D26IP_E2P)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IP, (NOINT << D22IP_MEI1IP)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IP, (INTA << D20IP_XHCI)), + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D20IP) = (INTA << D20IP_XHCI);
/* Device interrupt route registers */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IR, /* LPC */ - DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IR, /* EHCI */ - DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IR, /* PCIE */ - DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IR, /* HDA */ - DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IR, /* ME */ - DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D21IR, /* SIO */ - DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IR, /* XHCI */ - DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D23IR, /* SDIO */ - DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)), - - REG_SCRIPT_END -}; + RCBA32(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ + RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ + RCBA32(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ + RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ + RCBA32(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ + RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ + RCBA32(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ + RCBA32(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ +}
static void pch_enable_lpc(void) { @@ -76,7 +64,7 @@
void pch_early_init(void) { - reg_script_run_on_dev(PCH_DEV_LPC, pch_interrupt_init_script); + pch_route_interrupts();
pch_enable_lpc();
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46359 )
Change subject: soc/intel/broadwell/romstage/pch.c: Drop reg-script usage ......................................................................
Patch Set 7: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/46359/7/src/soc/intel/broadwell/rom... File src/soc/intel/broadwell/romstage/pch.c:
https://review.coreboot.org/c/coreboot/+/46359/7/src/soc/intel/broadwell/rom... PS7, Line 30: board specific grmlgrml
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46359 )
Change subject: soc/intel/broadwell/romstage/pch.c: Drop reg-script usage ......................................................................
soc/intel/broadwell/romstage/pch.c: Drop reg-script usage
Change-Id: I0e83eb724edc41514928482afe1bc90fb782e852 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46359 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/soc/intel/broadwell/romstage/pch.c 1 file changed, 21 insertions(+), 33 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index 9afb4e4..d68e17e 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -4,7 +4,6 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/smbus_host.h> -#include <reg_script.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pch.h> @@ -15,7 +14,8 @@ #include <soc/smbus.h> #include <soc/intel/broadwell/chip.h>
-const struct reg_script pch_interrupt_init_script[] = { +static void pch_route_interrupts(void) +{ /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP PCIE INTA -> PIRQA @@ -28,38 +28,26 @@ */
/* Device interrupt pin register (board specific) */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IP, - (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IP, (INTA << D29IP_E1P)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IP, - (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IP, (INTA << D27IP_ZIP)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D26IP, (INTA << D26IP_E2P)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IP, (NOINT << D22IP_MEI1IP)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IP, (INTA << D20IP_XHCI)), + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D20IP) = (INTA << D20IP_XHCI);
/* Device interrupt route registers */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IR, /* LPC */ - DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IR, /* EHCI */ - DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IR, /* PCIE */ - DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IR, /* HDA */ - DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IR, /* ME */ - DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D21IR, /* SIO */ - DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IR, /* XHCI */ - DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D23IR, /* SDIO */ - DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)), - - REG_SCRIPT_END -}; + RCBA32(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ + RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ + RCBA32(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ + RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ + RCBA32(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ + RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ + RCBA32(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ + RCBA32(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ +}
static void pch_enable_lpc(void) { @@ -76,7 +64,7 @@
void pch_early_init(void) { - reg_script_run_on_dev(PCH_DEV_LPC, pch_interrupt_init_script); + pch_route_interrupts();
pch_enable_lpc();
-
Angel Pons (Code Review) -
Nico Huber (Code Review)