Change in coreboot[master]: soc/amd/picasso/acpi: Change PCI0 BAR window

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50894 )

Change subject: soc/amd/picasso/acpi: Change PCI0 BAR window
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soc/amd/picasso/acpi: Change PCI0 BAR window

Picasso currently declares the BAR region between TOM and IO_APIC_ADDR.
This region includes MMCONF. We don't want to map any PCI BARs in this
region. This also matches what intel does.
See soc/intel/braswell/acpi/southcluster.asl for an example.

Signed-off-by: Raul E Rangel 
Change-Id: I9474fd6ac75a7245b3c35151c38186e913219bb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50894
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Marshall Dawson 
---
M src/soc/amd/picasso/acpi/sb_pci0_fch.asl
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
index ed321f3..0b253c9 100644
--- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
@@ -73,9 +73,9 @@
    CreateDWordField(CRES, ^MMIO._BAS, MM1B)
    CreateDWordField(CRES, ^MMIO._LEN, MM1L)

-	/* Declare memory between TOM1 and IOAPIC as available for PCI MMIO. */
+	/* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */
    MM1B = TOM1
-	Local0 = IO_APIC_ADDR /* This is the first MMIO device after TOM1. */
+	Local0 = CONFIG_MMCONF_BASE_ADDRESS
    Local0 -= TOM1
    MM1L = Local0