Change in coreboot[master]: soc/intel/tigerlake: Fix devices list in the DMAR DRHD structure

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52476 )

Change subject: soc/intel/tigerlake: Fix devices list in the DMAR DRHD structure
......................................................................

soc/intel/tigerlake: Fix devices list in the DMAR DRHD structure

The VT-d specification states that device scope for remapping hardware
unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list
of hardware unit definition structure. This change fixes the devices
list in the DMAR DRHD structure.

BUG=b:185631878
TEST=Built image and booted to kernel on Voxel board.

Signed-off-by: John Zhao 
Change-Id: I408fac7ff1185f4aa87bc4ffac7f25e31a4802b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52476
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/tigerlake/acpi.c
1 file changed, 14 insertions(+), 14 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c
index c60bcaa..c1f55f9 100644
--- a/src/soc/intel/tigerlake/acpi.c
+++ b/src/soc/intel/tigerlake/acpi.c
@@ -198,6 +198,20 @@
    	acpi_dmar_drhd_fixup(tmp, current);
    }

+	/* TCSS Thunderbolt root ports */
+	for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) {
+		uint64_t tbtbar = MCHBAR64(TBT0BAR + i * 8) & VTBAR_MASK;
+		bool tbten = MCHBAR32(TBT0BAR + i * 8) & VTBAR_ENABLED;
+		if (tbtbar && tbten) {
+			unsigned long tmp = current;
+
+			current += acpi_create_dmar_drhd(current, 0, 0, tbtbar);
+			current += acpi_create_dmar_ds_pci_br(current, 0, 7, i);
+
+			acpi_dmar_drhd_fixup(tmp, current);
+		}
+	}
+
    uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK;
    bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED;

@@ -216,20 +230,6 @@
    	acpi_dmar_drhd_fixup(tmp, current);
    }

-	/* TCSS Thunderbolt root ports */
-	for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) {
-		uint64_t tbtbar = MCHBAR64(TBT0BAR + i * 8) & VTBAR_MASK;
-		bool tbten = MCHBAR32(TBT0BAR + i * 8) & VTBAR_ENABLED;
-		if (tbtbar && tbten) {
-			unsigned long tmp = current;
-
-			current += acpi_create_dmar_drhd(current, 0, 0, tbtbar);
-			current += acpi_create_dmar_ds_pci_br(current, 0, 7, i);
-
-			acpi_dmar_drhd_fixup(tmp, current);
-		}
-	}
-
    /* Add RMRR entry */
    const unsigned long tmp = current;
    current += acpi_create_dmar_rmrr(current, 0,