Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31864
Change subject: soc/apollolake: Add UART0 ......................................................................
soc/apollolake: Add UART0
Change-Id: Id9a742144eba0f1d1544aafecf44d4730d055b4a Signed-off-by: Felix Singer felix.singer@9elements.com --- M src/soc/intel/apollolake/uart.c 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/31864/1
diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 66a1a1a..bda8aec 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -50,6 +50,13 @@ }, #else { + .console_index = 0, + .gpios = { + PAD_CFG_NF(GPIO_38, NATIVE, DEEP, NF1), /* UART0 RX */ + PAD_CFG_NF(GPIO_39, NATIVE, DEEP, NF1), /* UART0 TX */ + }, + }, + { .console_index = 1, .gpios = { PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31864 )
Change subject: soc/apollolake: Add UART0 ......................................................................
Patch Set 3:
Patch Set 1:
Btw. this is APL code, and GLK already has its own case. Are you implying that there are different versions of APL that have different UARTs exposed?
In my case, on Celeron N3350, I don't have UART2 but UART0
Hello Patrick Rudolph, Philipp Deppenwiese, Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31864
to look at the new patch set (#4).
Change subject: soc/apollolake: Add UART0 ......................................................................
soc/apollolake: Add UART0
In my case, on UPsquared board with Celeron N3350 CPU, I don't have UART2 but UART0.
Change-Id: Id9a742144eba0f1d1544aafecf44d4730d055b4a Signed-off-by: Felix Singer felix.singer@9elements.com --- M src/soc/intel/apollolake/uart.c 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/31864/4
Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31864 )
Change subject: soc/apollolake: Add UART0 ......................................................................
soc/apollolake: Add UART0
In my case, on UPsquared board with Celeron N3350 CPU, I don't have UART2 but UART0.
Change-Id: Id9a742144eba0f1d1544aafecf44d4730d055b4a Signed-off-by: Felix Singer felix.singer@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/31864 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/soc/intel/apollolake/uart.c 1 file changed, 7 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index a85ad1f..e8e2661 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -49,6 +49,13 @@ }, #else { + .console_index = 0, + .gpios = { + PAD_CFG_NF(GPIO_38, NATIVE, DEEP, NF1), /* UART0 RX */ + PAD_CFG_NF(GPIO_39, NATIVE, DEEP, NF1), /* UART0 TX */ + }, + }, + { .console_index = 1, .gpios = { PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */
-
Felix Singer (Code Review) -
Philipp Deppenwiese (Code Review)