[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock

[Subrata Banik (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Saurabh Mishra, Tarun.

Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
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Patch Set 32:

(3 comments)

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83354/comment/5b7fe8cb_d5aab816?usp... :
PS30, Line 141: 0xfe02c000
> We have matched with PTL FSP base address. This setting ensures the FSP's setting right IRQ to LPSS will be used by the coreboot.

why would FSP even bother to initialise the UART when we are setting UPD to `PchSerialIoSkipInit` to ensure FSP is not reprogramming the UART again.

Looking at the FSP code imo is not the correct practice for below reasons

1. what if tomorrow FSP decides to change this address again, how to ensure FSP and coreboot staus in sync?

2. not everyone has FSP source code to take a look.

It would be ideal if we could keep this minimal bootloader requirement in the FSP integration guide (if possible) or if FSP could publish its own memory map so that the BL knows which addresses to avoid. In my opinion, this is just another reserved range that belongs to PCH reserved memory, so there is no need to "align" to FSP. FSP and coreboot can have different addresses as long as FSP honors the UPD (PchSerialIoSkipInit) and does not touch the UART.

File src/soc/intel/pantherlake/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/70e5a49d_83c22594?usp... :
PS32, Line 19: #define SAF_BASE_ADDRESS	0xfa000000
> As per latest FAS, SAF BASE address is 0xfa000000.

Please refer to the doc number, I'm looking at 812562_PTL_FAS_Rev0p5

table 6.2 and section 6.2 as well.

File src/soc/intel/pantherlake/include/soc/pm.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/7a2bc4d7_a3b28189?usp... :
PS32, Line 45:  SMI_STS_BITS			32
             : #define  XHCI_SMI_STS_BIT		31
             : #define  ME_SMI_STS_BIT			30
             : #define  ESPI_SMI_STS_BIT		28
             : #define  GPIO_UNLOCK_SMI_STS_BIT	27
             : #define  SPI_SMI_STS_BIT		26
             : #define  SCC_SMI_STS_BIT		25
             : #define  MONITOR_STS_BIT		21
             : #define  PCI_EXP_SMI_STS_BIT		20
why not here as well