Change in coreboot[master]: soc/amd/common/acpi/pci_int.asl: Allow IRQ sharing

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52957 )

Change subject: soc/amd/common/acpi/pci_int.asl: Allow IRQ sharing
......................................................................

soc/amd/common/acpi/pci_int.asl: Allow IRQ sharing

PCI interrupts are level active low, so they can be shared.

BUG=b:184766519
TEST=Boot guybrush to OS with `pci=nomsi amd_iommu=off noapic`

Signed-off-by: Raul E Rangel 
Change-Id: I439337dd66fe56790406c6d603e73512c806a19d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52957
Reviewed-by: Felix Held 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/common/acpi/pci_int.asl
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved

diff --git a/src/soc/amd/common/acpi/pci_int.asl b/src/soc/amd/common/acpi/pci_int.asl
index 06ba0cc..306995d 100644
--- a/src/soc/amd/common/acpi/pci_int.asl
+++ b/src/soc/amd/common/acpi/pci_int.asl
@@ -2,14 +2,14 @@

/* PIC Possible Resource Values */
    Name(IRQP, ResourceTemplate() {
-		Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , , PIC){
+		Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , PIC){
    		1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15
    	}
    })

/* IO-APIC Possible Resource Values */
    Name(IRQI, ResourceTemplate() {
-		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , APIC) {
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , APIC) {
    		16, 17, 18, 19, 20, 21, 22, 23
    	}
    })
@@ -63,7 +63,7 @@
    				ResourceConsumer, \
    				Level, \
    				ActiveLow, \
-					Exclusive, , , NUMB) \
+					Shared, , , NUMB) \
    			{ 0 } \
    		} \
    		CreateDWordField(local0, NUMB._INT, IRQN) \