HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46235 )
Change subject: soc/intel/apollolake: Convert to ASL 2.0 syntax ......................................................................
soc/intel/apollolake: Convert to ASL 2.0 syntax
Change-Id: Ifc400433323630393566899dbeb5b0fac1a4bd00 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/apollolake/acpi/gpio.asl M src/soc/intel/apollolake/acpi/gpiolib.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/acpi/pch_hda.asl M src/soc/intel/apollolake/acpi/pcie_port.asl M src/soc/intel/apollolake/acpi/pmc_ipc.asl M src/soc/intel/apollolake/acpi/scs.asl 7 files changed, 87 insertions(+), 92 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/46235/1
diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl index 1fe58e1..f5795ef 100644 --- a/src/soc/intel/apollolake/acpi/gpio.asl +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -25,8 +25,8 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_COMM0_PID, PCR_PORTID_SHIFT, Local0) - Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS) + Local0 = GPIO_COMM0_PID << PCR_PORTID_SHIFT + RBAS = CONFIG_PCR_BASE_ADDRESS | Local0 Return (^RBUF) }
@@ -55,8 +55,8 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_COMM1_PID, PCR_PORTID_SHIFT, Local0) - Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS) + Local0 = GPIO_COMM1_PID << PCR_PORTID_SHIFT + RBAS = CONFIG_PCR_BASE_ADDRESS | Local0 Return (^RBUF) }
@@ -85,8 +85,8 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_COMM2_PID, PCR_PORTID_SHIFT, Local0) - Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS) + Local0 = GPIO_COMM2_PID << PCR_PORTID_SHIFT + RBAS = CONFIG_PCR_BASE_ADDRESS | Local0 Return (^RBUF) }
@@ -115,8 +115,8 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_COMM3_PID, PCR_PORTID_SHIFT, Local0) - Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS) + Local0 = GPIO_COMM3_PID << PCR_PORTID_SHIFT + RBAS = CONFIG_PCR_BASE_ADDRESS | Local0 Return (^RBUF) }
@@ -137,9 +137,9 @@ * local1 - to toggle Tx pin of Dw0 * local2 - Address of PERST */ - Store (Arg0, Local2) - Store (_SB.GPC0 (Local2), Local1) - Or (Local1, PAD_CFG0_TX_STATE, Local1) + Local2 = Arg0 + Local1 = _SB.GPC0 (Local2) + Local1 |= PAD_CFG0_TX_STATE _SB.SPC0 (Local2, Local1) }
@@ -151,9 +151,9 @@ * local1 - to toggle Tx pin of Dw0 * local2 - Address of PERST */ - Store (Arg0, Local2) - Store (_SB.GPC0 (Local2), Local1) - And (Local1, Not (PAD_CFG0_TX_STATE), Local1) + Local2 = Arg0 + Local1 = _SB.GPC0 (Local2) + Local1 &= ~PAD_CFG0_TX_STATE _SB.SPC0 (Local2, Local1) } } diff --git a/src/soc/intel/apollolake/acpi/gpiolib.asl b/src/soc/intel/apollolake/acpi/gpiolib.asl index 0ec9140..b7d14cc 100644 --- a/src/soc/intel/apollolake/acpi/gpiolib.asl +++ b/src/soc/intel/apollolake/acpi/gpiolib.asl @@ -6,7 +6,7 @@ Method (GPC0, 0x1, Serialized) { /* Arg0 - GPIO DW0 address */ - Store (Arg0, Local0) + Local0 = Arg0 OperationRegion (PDW0, SystemMemory, Local0, 4) Field (PDW0, AnyAcc, NoLock, Preserve) { TEMP, 32 @@ -19,19 +19,19 @@ { /* Arg0 - GPIO DW0 address */ /* Arg1 - Value for DW0 register */ - Store (Arg0, Local0) + Local0 = Arg0 OperationRegion (PDW0, SystemMemory, Local0, 4) Field (PDW0, AnyAcc, NoLock, Preserve) { TEMP,32 } - Store (Arg1, TEMP) + TEMP = Arg1 }
/* Get Pad Configuration DW1 register value */ Method (GPC1, 0x1, Serialized) { /* Arg0 - GPIO DW0 address */ - Store (Add (Arg0, 0x4), Local0) + Local0 = Arg0 + 4 OperationRegion (PDW1, SystemMemory, Local0, 4) Field (PDW1, AnyAcc, NoLock, Preserve) { TEMP, 32 @@ -44,12 +44,12 @@ { /* Arg0 - GPIO DW0 address */ /* Arg1 - Value for DW1 register */ - Store (Add (Arg0, 0x4), Local0) + Local0 = Arg0 + 4 OperationRegion (PDW1, SystemMemory, Local0, 4) Field(PDW1, AnyAcc, NoLock, Preserve) { TEMP,32 } - Store (Arg1, TEMP) + TEMP = Arg1 }
/* Get DW0 address of a given pad */ @@ -57,11 +57,9 @@ { /* Arg0 - GPIO portid */ /* Arg1 - GPIO pad offset relative to the community */ - Store (0, Local1) - Or( Or (ShiftLeft (Arg0, 16), CONFIG_PCR_BASE_ADDRESS), - Local1, Local1) - Or( Add (PAD_CFG_BASE, Multiply (Arg1, Multiply ( - GPIO_NUM_PAD_CFG_REGS, 4))), Local1, Local1) + Local1 = 0 + Local1 |= ((Arg0 << 16) | CONFIG_PCR_BASE_ADDRESS) + Local1 |= (PAD_CFG_BASE + (Arg1 * GPIO_NUM_PAD_CFG_REGS * 4)) Return (Local1) }
@@ -69,7 +67,7 @@ Method (CHSA, 0x1, Serialized) { /* Arg0 - GPIO pad offset relative to the community */ - Add (HOSTSW_OWN_REG_0, Multiply (Divide (Arg0, 32), 4), Local1) + Local1 = HOSTSW_OWN_REG_0 + ((Arg0 / 32) * 4) Return (Local1) }
@@ -78,10 +76,10 @@ { /* Arg0 - GPIO portid */ /* Arg1 - GPIO pad offset relative to the community */ - Store (CHSA (Arg1), Local1) + Local1 = CHSA (Arg1)
OperationRegion (SHO0, SystemMemory, Or ( Or - (CONFIG_PCR_BASE_ADDRESS, ShiftLeft (Arg0, 16)), Local1), 4) + (CONFIG_PCR_BASE_ADDRESS, (Arg0 << 16)), Local1), 4) Field (SHO0, AnyAcc, NoLock, Preserve) { TEMP, 32 } @@ -94,13 +92,13 @@ /* Arg0 - GPIO portid */ /* Arg1 - GPIO pad offset relative to the community */ /* Arg2 - Value for Host own register */ - Store (CHSA (Arg1), Local1) + Local1 = CHSA (Arg1)
OperationRegion (SHO0, SystemMemory, Or ( Or - (CONFIG_PCR_BASE_ADDRESS, ShiftLeft (Arg0, 16)), Local1), 4) + (CONFIG_PCR_BASE_ADDRESS, (Arg0 << 16)), Local1), 4) Field (SHO0, AnyAcc, NoLock, Preserve) { TEMP, 32 } - Store (Arg2, TEMP) + TEMP = Arg2 } } diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 1450983..df99154 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -78,12 +78,12 @@ CreateDwordField (MCRS, PM01._LEN, PLEN)
/* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ - And(_SB.PCI0.MCHC.TLUD, 0xFFF00000, PMIN) + PMIN = _SB.PCI0.MCHC.TLUD & 0xFFF00000 /* Read MMCONF base */ - And(_SB.PCI0.MCHC.MCNF, 0xF0000000, PMAX) + PMAX = _SB.PCI0.MCHC.MCNF & 0xF0000000
/* Calculate PCI MMIO Length */ - Add(Subtract(PMAX, PMIN), 1, PLEN) + PLEN = (PMAX - PMIN) + 1
/* Find GFX resource area in GCRS */ CreateDwordField(MCRS, STOM._MIN, GMIN) @@ -91,25 +91,25 @@ CreateDwordField(MCRS, STOM._LEN, GLEN)
/* Read BGSM */ - And(_SB.PCI0.MCHC.BGSM, 0xFFF00000, GMIN) + GMIN = _SB.PCI0.MCHC.BGSM & 0xFFF00000
/* Read TOLUD */ - And(_SB.PCI0.MCHC.TLUD, 0xFFF00000, GMAX) - Decrement(GMAX) - Add(Subtract(GMAX, GMIN), 1, GLEN) + GMAX = _SB.PCI0.MCHC.TLUD & 0xFFF00000 + GMAX-- + GLEN = (GMAX - GMIN) + 1
/* Patch PM02 range based on Memory Size */ - If (LEqual (A4GS, 0)) { + If (A4GS == 0) { CreateQwordField (MCRS, PM02._LEN, MSEN) - Store (0, MSEN) + MSEN = 0 } Else { CreateQwordField (MCRS, PM02._MIN, MMIN) CreateQwordField (MCRS, PM02._MAX, MMAX) CreateQwordField (MCRS, PM02._LEN, MLEN) /* Set 64bit MMIO resource base and length */ - Store (A4GS, MLEN) - Store (A4GB, MMIN) - Subtract (Add (MMIN, MLEN), 1, MMAX) + MLEN = A4GS + MMIN = A4GB + MMAX = (MMIN - MLEN) +1 }
Return (MCRS) diff --git a/src/soc/intel/apollolake/acpi/pch_hda.asl b/src/soc/intel/apollolake/acpi/pch_hda.asl index c3f862e..b23c541 100644 --- a/src/soc/intel/apollolake/acpi/pch_hda.asl +++ b/src/soc/intel/apollolake/acpi/pch_hda.asl @@ -29,19 +29,17 @@ * Arg2 - Function Index */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 0: Function Support Query * Returns a bitmask of functions supported. */ - If (LEqual (Arg2, Zero)) { + If (Arg2 == 0) { /* * NHLT Query only supported for revision 1 and * if NHLT address and length are set in NVS. */ - If (LAnd (LEqual (Arg1, One), - LAnd (LNotEqual (NHLA, Zero), - LNotEqual (NHLL, Zero)))) { + If ((Arg1 == 1) && (NHLA != 0) && (NHLL != 0)) { Return (Buffer (One) { 0x03 }) } Else { @@ -56,13 +54,13 @@ * * Returns a pointer to NHLT table in memory. */ - If (LEqual (Arg2, One)) { + If (Arg2 == 1) { CreateQWordField (NBUF, ^NHLT._MIN, NBAS) CreateQWordField (NBUF, ^NHLT._MAX, NMAS) CreateQWordField (NBUF, ^NHLT._LEN, NLEN) - Store (NHLA, NBAS) - Store (NHLA, NMAS) - Store (NHLL, NLEN) + NBAS = NHLA + NMAS = NHLA + NLEN = NHLL Return (NBUF) } } diff --git a/src/soc/intel/apollolake/acpi/pcie_port.asl b/src/soc/intel/apollolake/acpi/pcie_port.asl index f0f49f3..daa77e2 100644 --- a/src/soc/intel/apollolake/acpi/pcie_port.asl +++ b/src/soc/intel/apollolake/acpi/pcie_port.asl @@ -39,8 +39,8 @@ /* Define the PowerResource for PCIe slot */ Method (_STA, 0, Serialized) { - Store (PDS, PDST) - If (LEqual (PDS, 1)) { + PDST = PDS + If (PDS == 1) { Return (0xf) } Else { Return (0) @@ -49,7 +49,7 @@
Method (_ON, 0, Serialized) { - If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) { + If ((PDST == 1) && (\PRT0 != 0)) { /* Enter this condition if device * is connected */ @@ -57,25 +57,25 @@ /* De-assert PERST */ _SB.PCI0.PRDA (\PRT0)
- Store (0, BDQA) /* Set BLKDQDA to 0 */ - Store (0, BPLL) /* Set BLKPLLEN to 0 */ + BDQA = 0 /* Set BLKDQDA to 0 */ + BPLL = 0 /* Set BLKPLLEN to 0 */
/* Set L23_Rdy to Detect Transition * (L23R2DT) */ - Store (1, L23R) + L23R = 1 Sleep (16) - Store (0, Local0) + Local0 = 0
/* Delay for transition Detect * and link to train */ While (L23R) { - If (Lgreater (Local0, 4)) { + If (Local0 > 4) { Break } Sleep (16) - Increment (Local0) + Local0++ } } /* End PDS condition check */ } @@ -83,22 +83,22 @@ Method (_OFF, 0, Serialized) { /* Set L23_Rdy Entry Request (L23ER) */ - If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) { + If ((PDST == 1) && (\PRT0 != 0)) { /* enter this condition if device * is connected */ - Store (1, L23E) + L23E = 1 Sleep (16) - Store (0, Local0) + Local0 = 0 While (L23E) { - If (Lgreater (Local0, 4)) { + If (Local0 > 4) { Break } Sleep (16) - Increment (Local0) + Local0++ } - Store (1, BDQA) /* Set BLKDQDA to 1 */ - Store (1, BPLL) /* Set BLKPLLEN to 1 */ + BDQA = 1 /* Set BLKDQDA to 1 */ + BPLL = 1 /* Set BLKPLLEN to 1 */
/* Assert PERST */ _SB.PCI0.PRAS (\PRT0) diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl index 7611a2d..7b0e497 100644 --- a/src/soc/intel/apollolake/acpi/pmc_ipc.asl +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -30,15 +30,15 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^IBAR._BAS, IBAS) - Store (PMC_BAR0, IBAS) + IBAS = PMC_BAR0
CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) - Store (MCH_BASE_ADDRESS + MAILBOX_DATA, MDBA) + MDBA = MCH_BASE_ADDRESS + MAILBOX_DATA CreateDwordField (^RBUF, ^MINF._BAS, MIBA) - Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA) + MIBA = MCH_BASE_ADDRESS + MAILBOX_INTF
CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) - Store (SRAM_BASE_0, SBAS) + SBAS = SRAM_BASE_0
Return (^RBUF) } diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl index 1ee70ad..f7de2dc 100644 --- a/src/soc/intel/apollolake/acpi/scs.asl +++ b/src/soc/intel/apollolake/acpi/scs.asl @@ -4,8 +4,7 @@ /* 0xD6- is the port address */ /* 0x600- is the dynamic clock gating control register offset (GENR) */ OperationRegion (SBMM, SystemMemory, - Or ( Or (CONFIG_PCR_BASE_ADDRESS, - ShiftLeft(0xD6, PCR_PORTID_SHIFT)), 0x0600), 0x18) + (CONFIG_PCR_BASE_ADDRESS | (0xD6 << PCR_PORTID_SHIFT) | 0x0600), 0x18) Field (SBMM, DWordAcc, NoLock, Preserve) { GENR, 32, @@ -23,10 +22,10 @@ */ Method (SCPG, 2, Serialized) { - if (LEqual(Arg0, 0x1)) { - Or (^GENR, Arg1, ^GENR) - } ElseIf (LEqual(Arg0, 0x0)){ - And (^GENR, Arg1, ^GENR) + if (Arg0 == 0x1) { + ^GENR |= Arg1 + } ElseIf (Arg0 == 0x0){ + ^GENR &= Arg1 } }
@@ -44,13 +43,13 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 9: Device Readiness Durations * Returns a package of five integers covering * various device related delays in PCIe Base Spec. */ - If (LEqual (Arg2, 9)) { + If ((Arg2 == 9) { /* * Function 9 support for revision 3. * ECN link for function definitions @@ -58,7 +57,7 @@ * specification_documents/ * ECN_fw_latency_optimization_final.pdf] */ - If (LEqual (Arg1, 3)) { + If (Arg1 == 3) { /* * Integer 0: FW reset time. * Integer 1: FW data link up time. @@ -118,14 +117,14 @@ Method (_INI, 0) { /* Check SDCard CD port is valid */ - If (LAnd (LNotEqual (\SCDP, 0), LNotEqual (\SCDO, 0) )) + If ((\SCDP != 0) && (\SCDO != 0)) { /* Store DW0 address of SD_CD */ - Store (GDW0 (\SCDP, \SCDO), SCD0) + SCD0 = GDW0 (\SCDP, \SCDO) /* Get the current SD_CD ownership */ - Store (_SB.GHO (\SCDP, \SCDO), Local0) + Local0 = _SB.GHO (\SCDP, \SCDO) /* Set host ownership as GPIO in HOSTSW_OWN reg */ - Or (Local0, ShiftLeft (1, Mod (\SCDO, 32)), Local0) + Local0 |= 1 << (\SCDO % 32) _SB.SHO (\SCDP, \SCDO, Local0) } } @@ -133,20 +132,20 @@ Method (_PS0, 0, NotSerialized) { /* Check SDCard CD port is valid */ - If (LAnd (LNotEqual (\SCDP, 0), LNotEqual (\SCDO, 0) )) + If ((\SCDP != 0) && (\SCDO != 0)) { /* Store DW0 into local0 to get rxstate of GPIO */ - Store (_SB.GPC0 (SCD0), Local0) + Local0 = _SB.GPC0 (SCD0) /* Extract rxstate [bit 1] of sdcard card detect pin */ - And (Local0, PAD_CFG0_RX_STATE, Local0) + Local0 &= PAD_CFG0_RX_STATE /* If the sdcard is present, rxstate is low. * If sdcard is not present, rxstate is High. * Write the inverted value of rxstate to GRR3. */ - If (LEqual (Local0, 0)) { - Store (1, ^^GRR3) + If (Local0 == 0) { + ^^GRR3 = 1 } Else { - Store (0, ^^GRR3) + ^^GRR3 = 0 } Sleep (2) } @@ -155,7 +154,7 @@ Method (_PS3, 0, NotSerialized) { /* Clear GRR3 to Power Gate SD Controller */ - Store (0, ^^GRR3) + ^^GRR3 = 0 }
Device (CARD)
Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46235
to look at the new patch set (#2).
Change subject: soc/intel/apollolake: Convert to ASL 2.0 syntax ......................................................................
soc/intel/apollolake: Convert to ASL 2.0 syntax
Change-Id: Ifc400433323630393566899dbeb5b0fac1a4bd00 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/apollolake/acpi/gpio.asl M src/soc/intel/apollolake/acpi/gpiolib.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/acpi/pch_hda.asl M src/soc/intel/apollolake/acpi/pcie_port.asl M src/soc/intel/apollolake/acpi/pmc_ipc.asl M src/soc/intel/apollolake/acpi/scs.asl 7 files changed, 87 insertions(+), 92 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/46235/2
Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46235
to look at the new patch set (#3).
Change subject: soc/intel/apollolake: Convert to ASL 2.0 syntax ......................................................................
soc/intel/apollolake: Convert to ASL 2.0 syntax
Change-Id: Ifc400433323630393566899dbeb5b0fac1a4bd00 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/apollolake/acpi/gpio.asl M src/soc/intel/apollolake/acpi/gpiolib.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/acpi/pch_hda.asl M src/soc/intel/apollolake/acpi/pcie_port.asl M src/soc/intel/apollolake/acpi/pmc_ipc.asl M src/soc/intel/apollolake/acpi/scs.asl 7 files changed, 87 insertions(+), 92 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/46235/3
-
HAOUAS Elyes (Code Review)