[S] Change in coreboot[main]: soc/intel/pantherlake: Bind SoC config VR settings to respective UPD

[Subrata Banik (Code Review)]

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N.

Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85131?usp=email )

Change subject: soc/intel/pantherlake: Bind SoC config VR settings to respective UPD
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Patch Set 12: Code-Review+2

(1 comment)

Patchset:

PS6:
> We needed to wait for 3015 for the `CepEnable` UPD to even exist.
>
> https://review.coreboot.org/c/coreboot/+/86258 introduces 3015 Partial headers. However, in order to fully utilize this feature, we integrated a CL from a subsequent version of the FSP, which exports some extra UPDs. While UPDs were present in version 3015, they are not naively accessible .
>
> To legitimate CL 86258, we can port the extra UPD exportation CL to Google repository once a 3015 is available in this repository.

Can you please push the UPD changes in Chrome-Internal and get the review going? Till then, if possible, please hold this CL on the patch train. After the FSP 3-15 merge is done, we’ll start with eSOL.