[S] Change in coreboot[master]: soc/intel/apl: Fix programming temporary MTRR on GLK

[Arthur Heymans (Code Review)]

Attention is currently required from: Sean Rhodes.

Hello Sean Rhodes,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/73836

to look at the new patch set (#3).

Change subject: soc/intel/apl: Fix programming temporary MTRR on GLK
......................................................................

soc/intel/apl: Fix programming temporary MTRR on GLK

Programming MTRR happens later in the
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT codepath.
fast_spi_cache_bios_region() assumes an existing MTRR solution from
x86_setup_mtrrs_with_detect().

This fixes a problem introduced by 829e8e6 "soc/intel: Use common
codeflow for MP init".

Change-Id: I9b6130cf76317440ebe7a7a53e460e2b658d198e
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/apollolake/cpu.c
1 file changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/73836/3