Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86499?usp=email )
Change subject: tmp ......................................................................
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tested: coreboot -> EDK2 -> Linux v6.6.4 4x USB backpanel block PCH PCIe x4 Slot 1 PCH PCIe x2 Slot 2 PCH PCIe x4 Slot 3 PCH PCIe M.2 Key M Slot 1 PCH PCIe M.2 Key M Slot 2 2x USB-3.2 Slots vertical 2x USB-3.2 slots Backplane (below the GBE slot) 2x USB-3.2 Slots Backplane (Quad stack) 2x USB-2.0 Slots Backplane (Quad stack) 2x Displayport Backpanel 2x SATA (vertical connector) 1x SATA Direct connect
not tested: PCH PCIe M.2 Key M Slot 3 (on the bottom side of the board) PS2 (keyboard/mouse) 1x USB-3.2 FP Type-A 1x USB-3.2 FP Type-C
not working: GBE (PCIe device shows up though) 2x HDMI ports (does not work on original BIOS either) M.2 CNvi (does not work on original BIOS either)
Signed-off-by: Maximilian Brune maximilian.brune@9elements.com Change-Id: Ie66d4a5ba57fda28bcadb43cc8d3d810ced3f6d0 --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Kconfig.name M src/mainboard/intel/adlrvp/Makefile.inc M src/mainboard/intel/adlrvp/devicetree_s.cb R src/mainboard/intel/adlrvp/gpio_adl_s.c M src/mainboard/intel/adlrvp/include/baseboard/variants.h M src/mainboard/intel/adlrvp/memory.c M src/mainboard/intel/adlrvp/ramstage.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 11 files changed, 98 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/86499/1
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index a7ce0e1..8b63431 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -87,6 +87,14 @@ select SOC_INTEL_ALDERLAKE_PCH_S select INTEL_CAR_NEM
+config BOARD_INTEL_ADLRVP_RPL_S_DDR5_UDIMM_1DPC + select BOARD_INTEL_ADLRVP_COMMON + select DRIVERS_UART_8250IO + select MAINBOARD_USES_IFD_EC_REGION + select MAINBOARD_USES_IFD_GBE_REGION + select SOC_INTEL_RAPTORLAKE_PCH_S + select INTEL_GMA_HAVE_VBT + config BOARD_INTEL_ADLRVP_N select BOARD_INTEL_ADLRVP_COMMON select DRIVERS_UART_8250IO @@ -127,6 +135,7 @@
config VARIANT_DIR default "adlrvp_s_ddr5_udimm_1dpc" if BOARD_INTEL_ADLRVP_S_DDR5_UDIMM_1DPC + default "adlrvp_rpl_s_ddr5_udimm_1dpc" if BOARD_INTEL_ADLRVP_RPL_S_DDR5_UDIMM_1DPC default "adlrvp_p" if BOARD_INTEL_ADLRVP_P default "adlrvp_p_ext_ec" if BOARD_INTEL_ADLRVP_P_EXT_EC default "adlrvp_rpl" if BOARD_INTEL_ADLRVP_RPL @@ -158,7 +167,7 @@ config DEVICETREE default "devicetree_m.cb" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC default "devicetree_n.cb" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC - default "devicetree_s.cb" if BOARD_INTEL_ADLRVP_S_DDR5_UDIMM_1DPC + default "devicetree_s.cb" if BOARD_INTEL_ADLRVP_S_DDR5_UDIMM_1DPC || BOARD_INTEL_ADLRVP_RPL_S_DDR5_UDIMM_1DPC default "devicetree.cb"
config OVERRIDE_DEVICETREE @@ -169,7 +178,7 @@
choice prompt "ON BOARD EC" - default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_RPL || BOARD_INTEL_ADLRVP_S_DDR5_UDIMM_1DPC + default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_RPL || BOARD_INTEL_ADLRVP_S_DDR5_UDIMM_1DPC || BOARD_INTEL_ADLRVP_RPL_S_DDR5_UDIMM_1DPC default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_RPL_EXT_EC help This option allows you to select the on board EC to use. diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name index 8696776..7700689 100644 --- a/src/mainboard/intel/adlrvp/Kconfig.name +++ b/src/mainboard/intel/adlrvp/Kconfig.name @@ -27,3 +27,7 @@
config BOARD_INTEL_ADLRVP_RPL_EXT_EC bool "Raptorlake silicon with Alderlake-P RVP and Chrome EC" + +config BOARD_INTEL_ADLRVP_RPL_S_DDR5_UDIMM_1DPC + bool "Raptorlake silicon with Alderlake-S RVP DDR5 UDIMM 1DPC" + diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index 1303698..7891609 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -12,7 +12,8 @@ ramstage-y += gpio_n.c else ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y) bootblock-y += early_gpio_s.c -ramstage-y += gpio_s.c +#ramstage-y += gpio_rpl_s_bkc.c +ramstage-y += gpio_rpl_s.c else bootblock-y += early_gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/intel/adlrvp/devicetree_s.cb b/src/mainboard/intel/adlrvp/devicetree_s.cb index 23560d0..f2268ed 100644 --- a/src/mainboard/intel/adlrvp/devicetree_s.cb +++ b/src/mainboard/intel/adlrvp/devicetree_s.cb @@ -1,21 +1,65 @@ chip soc/intel/alderlake + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + register "serial_io_gspi_cs_mode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "serial_io_gspi_cs_state" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on - device ref igpu on - # DDI_PORT_A: Combo PHY A # ADL-S RVP UDIMM 1DPC eDP1.4 Connector - # DDI_PORT_1: Combo PHY B # ADL-S RVP UDIMM 1DPC HDMI 1.4b CRLS - # DDI_PORT_2: Combo PHY C # ADL-S RVP UDIMM 1DPC DP1.4a Connector - # DDI_PORT_3: Combo PHY D # ADL-S RVP UDIMM 1DPC HDMI 2.0b ALS - # DDI_PORT_4: Combo PHY E # ADL-S RVP UDIMM 1DPC DP1.4a Connector - # Enable eDP in PortA #TODO test - #register "ddi_portA_config" = "1" - #[DDI_PORT_A] = DDI_ENABLE_HPD - register "ddi_ports_config" = "{ - [DDI_PORT_1] = DDI_ENABLE_HPD, - [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, - [DDI_PORT_3] = DDI_ENABLE_HPD, - [DDI_PORT_4] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, - }" - end device ref sata on register "sata_salp_support" = "1" register "sata_ports_enable" = "{ @@ -30,12 +74,5 @@ [7] = 1, }" end - device ref xhci on - # Configure overcurrent for USB Ports - register "usb2_ports[6]" = "USB2_PORT_MID(OC7)" # USB3/2 Type A port7 - register "usb2_ports[9]" = "USB2_PORT_MID(OC7)" # USB3/2 Type A port10 - register "usb2_ports[10]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port11 - register "usb2_ports[12]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port13 - end end end diff --git a/src/mainboard/intel/adlrvp/gpio_s.c b/src/mainboard/intel/adlrvp/gpio_adl_s.c similarity index 100% rename from src/mainboard/intel/adlrvp/gpio_s.c rename to src/mainboard/intel/adlrvp/gpio_adl_s.c diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 50aed48..61c388e 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -27,6 +27,8 @@ ADL_N_LP5 = 0x7, /* ADL-S DDR5 RVP 1DPC */ ADL_S_DDR5_1DPC = 0x2B, + /* RPL-S DDR5 RVP 1DPC */ + RPL_S_DDR5_1DPC = 0x39, };
/* Functions to configure GPIO as per variant schematics */ diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index 424c499..a86d2c7 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -394,6 +394,8 @@ return &adln_lp5_mem_config; case ADL_S_DDR5_1DPC: return &adls_ddr5_1dpc_mem_config; + case RPL_S_DDR5_1DPC: + return &adls_ddr5_1dpc_mem_config; default: die("unsupported board id : 0x%x\n", board_id); } diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c index d8282da..533ed35 100644 --- a/src/mainboard/intel/adlrvp/ramstage.c +++ b/src/mainboard/intel/adlrvp/ramstage.c @@ -62,7 +62,8 @@ }
#if (!(CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) \ - || CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_S_DDR5_UDIMM_1DPC))) + || CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_S_DDR5_UDIMM_1DPC) \ + || CONFIG(BOARD_INTEL_ADLRVP_RPL_S_DDR5_UDIMM_1DPC)))
static const struct board_id_iom_port_config { int board_id; @@ -100,7 +101,8 @@
/* Skip filling aux bias gpio pads for Windows SKUs */ #if (!(CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) \ - || CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_S_DDR5_UDIMM_1DPC))) + || CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_S_DDR5_UDIMM_1DPC) \ + || CONFIG(BOARD_INTEL_ADLRVP_RPL_S_DDR5_UDIMM_1DPC))) variant_update_typec_init_config(); #endif } diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 87a545e..67a9776 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -92,6 +92,7 @@ case ADL_P_DDR4_2: case ADL_P_DDR5_1: case ADL_S_DDR5_1DPC: + case RPL_S_DDR5_1DPC: memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated); break; case ADL_P_DDR5_2: diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index b1e90fa..2ff8808 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -771,6 +771,15 @@ * Set this to 0 in order to disable hwp scalability tracking. */ bool enable_hwp_scalability_tracking; + + /* + * Set maximum speed (generation) for DMI Link between CPU and PCH + * 0 (Default): automatically determine the maximum DMI Gen supported + * 1: DMI Gen1 Link speed + * 2: DMI Gen2 Link speed + * ... + */ + uint8_t dmi_max_link_speed; };
typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 84f83e3..62c99b0 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -236,6 +236,9 @@
/* Skip MBP HOB */ m_cfg->SkipMbpHob = !CONFIG(FSP_PUBLISH_MBP_HOB); + + /* Set maximum DMI link speed defined by the generation (e.g. Gen1, Gen2, Gen3 ...) */ + m_cfg->DmiMaxLinkSpeed = config->dmi_max_link_speed; }
static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
-
Maximilian Brune (Code Review)