Change in coreboot[master]: soc/intel/tigerlake: Add known GPIO virtual wire information - coreboot-gerrit

4 May 2021


      Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52589 )
Change subject: soc/intel/tigerlake: Add known GPIO virtual wire information
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Patch Set 6: Code-Review+2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icc4581e61ee904cbd998738962d360a58d24bc35
Gerrit-Change-Number: 52589
Gerrit-PatchSet: 6
Gerrit-Owner: Tim Wawrzynczak twawrzynczak@chromium.org
Gerrit-Reviewer: Furquan Shaikh furquan@google.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Attention: Tim Wawrzynczak twawrzynczak@chromium.org
Gerrit-Attention: Patrick Rudolph siro@das-labor.org
Gerrit-Comment-Date: Tue, 04 May 2021 07:23:21 +0000
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