[M] Change in coreboot[main]: soc/intel/xeon_sp: Initial support for PCI multi segment groups

[Patrick Rudolph (Code Review)]

Attention is currently required from: Annie Chen, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Naresh Solanki, Nill Ge, Patrick Rudolph, Shuo Liu, TangYiwei, Tim Chu.

Hello Annie Chen, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Naresh Solanki, Nill Ge, Shuo Liu, TangYiwei, Tim Chu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/79878?usp=email

to look at the new patch set (#7).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/xeon_sp: Initial support for PCI multi segment groups
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soc/intel/xeon_sp: Initial support for PCI multi segment groups

Add PCI enumeration support by reading the PCIeSegment reported in the
FSP HOB and add it when creating the PCI domain for each stack.

The PCI enumeration will be able to scan the additional PCI segment
groups and properly handle those devices. Code that still hardcodes
B:D:F numbers will not work when PCI multi segment support is enabled
and need to be updated in future commits.

In addition ACPI code generation needs to take PCI segment groups
into account.

Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/spr/ioat.c
3 files changed, 48 insertions(+), 17 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/79878/7