Change in coreboot[master]: soc/intel/skylake: Enable UART debug controller on S3 resume

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20886

Change subject: soc/intel/skylake: Enable UART debug controller on S3 resume
......................................................................

soc/intel/skylake: Enable UART debug controller on S3 resume

1. Add a new variable to GNVS to store information during S3 suspend
whether UART debug port controller is enabled.

2. On resume, read stored GNVS variable to decide if UART debug port
controller needs to be initialized.

3. Provide helpers functions required by intel/common UART driver for
enabling controller on S3 resume.

BUG=b:64030366
TEST=Verified behavior with different combinations:
1. Serial console enabled in coreboot: No change in behavior.
2. Serial console enabled only in kernel: Coreboot initializes debug
controller on S3 resume.
3. Serial console not enabled in coreboot and kernel: Coreboot skips
initialization of debug controller on S3 resume.

Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c
---
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/acpi/globalnvs.asl
M src/soc/intel/skylake/include/soc/nvs.h
M src/soc/intel/skylake/smihandler.c
M src/soc/intel/skylake/uart.c
5 files changed, 27 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/20886/1

diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 7f618d4..baf6f01 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -76,6 +76,7 @@
 smm-y += smihandler.c
 smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
 smm-$(CONFIG_UART_DEBUG) += uart_debug.c
+smm-y += uart.c

postcar-y += memmap.c
 postcar-$(CONFIG_UART_DEBUG) += uart_debug.c
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index d06269f..8a7606c 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -66,6 +66,7 @@
    CID1,	16,	// 0x3d - Wifi Country Identifier
    U2WE,	16,	// 0x3f - USB2 Wake Enable Bitmap
    U3WE,	8,	// 0x41 - USB3 Wake Enable Bitmap
+	UIOR,	8,	// 0x42 - UART debug controller init on S3 resume

/* ChromeOS specific */
    Offset (0x100),
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 4ca3d22..8272336 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -57,7 +57,8 @@
    u16	cid1; /* 0x3d - Wifi Country Identifier */
    u16	u2we; /* 0x3f - USB2 Wake Enable Bitmap */
    u8	u3we; /* 0x41 - USB3 Wake Enable Bitmap */
-	u8	unused[190];
+	u8	uior; /* 0x42 - UART debug controller init on S3 resume */
+	u8	unused[189];

/* ChromeOS specific (0x100 - 0xfff) */
    chromeos_acpi_t chromeos;
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index c4c4a7b..d87994e 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -24,6 +24,7 @@
 #include <elog.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/pcr.h>
+#include <intelblocks/uart.h>
 #include <delay.h>
 #include <device/pci_def.h>
 #include <elog.h>
@@ -165,6 +166,8 @@
    case ACPI_S3:
    	printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");

+		gnvs->uior = uart_debug_controller_is_initialized();
+
    	/* Invalidate the cache before going to S3 */
    	wbinvd();
    	break;
diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c
index 07326d5..f254400 100644
--- a/src/soc/intel/skylake/uart.c
+++ b/src/soc/intel/skylake/uart.c
@@ -14,16 +14,19 @@
  * GNU General Public License for more details.
  */

+#include <cbmem.h>
 #include <device/pci.h>
 #include <intelblocks/uart.h>
 #include <soc/iomap.h>
+#include <soc/nvs.h>
 #include <soc/pci_devs.h>

-static int pch_uart_is_debug(struct device *dev)
+bool pch_uart_is_debug(struct device *dev)
 {
    return dev->path.pci.devfn == PCH_DEVFN_UART2;
 }

+#if ENV_RAMSTAGE
 void pch_uart_read_resources(struct device *dev)
 {
    pci_dev_read_resources(dev);
@@ -38,3 +41,19 @@
    		IORESOURCE_FIXED;
    }
 }
+#endif
+
+bool pch_uart_init_debug_controller_on_resume(void)
+{
+	global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+
+	if (gnvs)
+		return !!gnvs->uior;
+
+	return false;
+}
+
+device_t pch_uart_get_debug_controller(void)
+{
+	return PCH_DEV_UART2;
+}