Change in coreboot[master]: mb/google/hatch/var/ambassador: configure FSP option PcieRpSlotImplem...

[Matthew Ziegelbaum (Code Review)]

Matthew Ziegelbaum has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47685 )

Change subject: mb/google/hatch/var/ambassador: configure FSP option PcieRpSlotImplemented
......................................................................

mb/google/hatch/var/ambassador: configure FSP option PcieRpSlotImplemented

Ambassador is similar to puff. This change matches the
PcieRpSlotImplemented configuration with Puff's, originally made for
Puff in https://review.coreboot.org/c/coreboot/+/39986.

Signed-off-by: Matt Ziegelbaum 
Change-Id: I5b6246f58c10e03a0d02278ad3621ded39bb6d6e
---
M src/mainboard/google/hatch/variants/ambassador/overridetree.cb
1 file changed, 4 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/47685/1

diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb
index 7b46153..7cc920d 100644
--- a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb
@@ -402,8 +402,11 @@
    			register "device_index" = "0"
    			device pci 00.0 on end
    		end
+			register "PcieRpSlotImplemented[6]" = "1"
    	end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
    	device pci 1e.3 off end # GSPI #1
    end

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47685 )

Change subject: mb/google/hatch/var/ambassador: configure FSP option PcieRpSlotImplemented
......................................................................

Patch Set 1: Code-Review+2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47685 )

Change subject: mb/google/hatch/var/ambassador: configure FSP option PcieRpSlotImplemented
......................................................................

mb/google/hatch/var/ambassador: configure FSP option PcieRpSlotImplemented

Ambassador is similar to puff. This change matches the
PcieRpSlotImplemented configuration with Puff's, originally made for
Puff in https://review.coreboot.org/c/coreboot/+/39986.

Signed-off-by: Matt Ziegelbaum 
Change-Id: I5b6246f58c10e03a0d02278ad3621ded39bb6d6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47685
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/mainboard/google/hatch/variants/ambassador/overridetree.cb
1 file changed, 4 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb
index 7b46153..7cc920d 100644
--- a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb
@@ -402,8 +402,11 @@
    			register "device_index" = "0"
    			device pci 00.0 on end
    		end
+			register "PcieRpSlotImplemented[6]" = "1"
    	end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
    	device pci 1e.3 off end # GSPI #1
    end