[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Trim GPIO comments

[Weimin Wu (Code Review)]

Weimin Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79321?usp=email )

Change subject: mb/google/nissa/var/anraggar: Trim GPIO comments
......................................................................

mb/google/nissa/var/anraggar: Trim GPIO comments

Trim all GPIO comments like "origin ==> current".

BUG=b:304920262
TEST=pass building

Change-Id: I05daa4df16b6da3d3f971b75c7c467032e3f854d
Signed-off-by: Weimin Wu 
---
M src/mainboard/google/brya/variants/anraggar/gpio.c
1 file changed, 13 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/79321/1

diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c
index bc9e89d..8e0b76b 100644
--- a/src/mainboard/google/brya/variants/anraggar/gpio.c
+++ b/src/mainboard/google/brya/variants/anraggar/gpio.c
@@ -14,16 +14,16 @@
    /* A18 : NC ==> HDMI_HPD_SRC*/
    PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),

-	/* A20 : DDSP_HPD2 ==> EC_SOC_HDMI_HPD ==> NC */
+	/* A20 : DDSP_HPD2 ==> NC */
    PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
-	/* A21 : GPP_A21 ==> USB_C1_AUX_DC_P ==> NC */
+	/* A21 : GPP_A21 ==> NC */
    PAD_NC_LOCK(GPP_A21, NONE, LOCK_CONFIG),
-	/* A22 : GPP_A22 ==> USB_C1_AUX_DC_N ==> NC */
+	/* A22 : GPP_A22 ==> NC */
    PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG),

-	/* B5  : I2C2_SDA ==> SOC_I2C_SUB_SDA ==> MIPI_WCAM_SDA */
+	/* B5  : I2C2_SDA ==> MIPI_WCAM_SDA */
    PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
-	/* B6  : I2C2_SCL ==> SOC_I2C_SUB_SCL ==> MIPI_WCAM_SCL */
+	/* B6  : I2C2_SCL ==> MIPI_WCAM_SCL */
    PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG),

/* B11 : NC ==> EN_PP3300_WLAN_X*/
@@ -31,14 +31,14 @@

/* D6 : NC ==> WWAN_PWR_ENABLE */
    PAD_CFG_GPO(GPP_D6, 1, DEEP),
-	/* D8  : SRCCLKREQ3# ==> SD_CLKREQ_ODL ==> NC */
+	/* D8  : SRCCLKREQ3# ==> NC */
    PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
    /* D13 : NC ==> EN_PP1800_WCAM_X */
    PAD_CFG_GPO_LOCK(GPP_D13, 1, LOCK_CONFIG),

-	/* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL ==> NC */
+	/* E20 : DDP2_CTRLCLK ==> NC */
    PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
-	/* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP ==> GPP_E21_STRAP */
+	/* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */
    PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG),

/* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */
@@ -52,22 +52,22 @@
    PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
    /* F18 : THC1_SPI2_INT# ==> EN_PP2800_AFVDD */
    PAD_CFG_GPO(GPP_F18, 0, DEEP),
-	/* F23 : V1P05_CTRL ==> V1P05EXT_CTRL ==> NC*/
+	/* F23 : V1P05_CTRL ==> NC*/
    PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG),

-	/* H12 : UART0_RTS# ==> SD_PERST_L ==> NC*/
+	/* H12 : UART0_RTS# ==> NC*/
    PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
-	/* H13 : UART0_CTS# ==> EN_PP3300_SD_X ==> NC */
+	/* H13 : UART0_CTS# ==> NC */
    PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
    /* H15 : DDPB_CTRLCLK ==> HDMI_DDC_SCL */
    PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
    /* H17 : DDPB_CTRLDATA ==> HDMI_DDC_SDA */
    PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),

-	/* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R ==> NC */
+	/* R6 : DMIC_CLK_A_1A ==> NC */
    PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG),
-	/* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA ==> NC */
+	/* R7 : DMIC_DATA_1A ==> NC */
    PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG),
 };