[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PLL and clock init support

[Guangjie Song (Code Review)]

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu.

Guangjie Song has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84495?usp=email )

Change subject: soc/mediatek/mt8196: Add PLL and clock init support
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Patch Set 27:

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/84495/comment/905b9721_0ef72dad?usp... :
PS26, Line 7: Clock
> clock

Done

File src/soc/mediatek/mt8196/pll.c:

https://review.coreboot.org/c/coreboot/+/84495/comment/079f99cc_baa1e849?usp... :
PS13, Line 1196: 30
> Agree with Yu-Ping. […]

Done

File src/soc/mediatek/mt8196/pll.c:

https://review.coreboot.org/c/coreboot/+/84495/comment/9c6f79ad_0419d09e?usp... :
PS26, Line 863: (
> No need for the extra `()`

Done

https://review.coreboot.org/c/coreboot/+/84495/comment/03ee83f0_0194e401?usp... :
PS26, Line 1176: mmvote_mtcmos_mtcmos_table
> `child_idx` is the same as `parent_idx`. […]

it is expected
now we remove the array to save space and initialize the corresponding registers according to the config rules