[L] Change in coreboot[main]: soc/mediatek/mt8196: Add srclken_rc drivers

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, ot_song fan.

Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85842?usp=email )

Change subject: soc/mediatek/mt8196: Add srclken_rc drivers
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Patch Set 4:

(6 comments)

File src/soc/mediatek/mt8196/include/soc/srclken_rc.h:

https://review.coreboot.org/c/coreboot/+/85842/comment/5ab480e6_694ae65d?usp... :
PS4, Line 86: 
Add `check_member(mtk_rc_regs, rc_spi_sta_0, 0x10c);`.

File src/soc/mediatek/mt8196/include/soc/srclken_rc.h:

https://review.coreboot.org/c/coreboot/+/85842/comment/8c5c903f_424b3e19?usp... :
PS1, Line 126: _M
> DCXO_FPM_CTRL_M means dcxo_fpm_ctrl_mode. […]

Ack

File src/soc/mediatek/mt8196/srclken_rc.c:

https://review.coreboot.org/c/coreboot/+/85842/comment/835b8584_69f77c77?usp... :
PS1, Line 265: code flow ASSERT already
> This code flow will call ASSERT(). […]

Do you mean the `assert(id < MAX_CHN_NUM)` call? How's that related to the rc_mxx_req_sta_0 register?

File src/soc/mediatek/mt8196/srclken_rc.c:

https://review.coreboot.org/c/coreboot/+/85842/comment/77594ad9_cb5d187c?usp... :
PS4, Line 474: REQ_TO_SPMI_P_MASK_SHFT
`REQ_TO_SPMI_P_SUBSYS` is already a 32-bit value, do we still need `REQ_TO_SPMI_P_MASK_SHFT`? If you still prefer keeping it, please use `WRITE32_BITFIELDS`.

https://review.coreboot.org/c/coreboot/+/85842/comment/312ac7c4_b9fe7eba?usp... :
PS4, Line 477: write32
Can we use `WRITE32_BITFIELDS`?

https://review.coreboot.org/c/coreboot/+/85842/comment/6cf6f938_e382bb9f?usp... :
PS4, Line 527: 0xA
```
mask = SW_SRCLKEN_FPM_MSK << 1 | SW_SRCLKEN_BBLPM_MSK << 3;
state = (fpm & SW_SRCLKEN_FPM_MSK) << 1 |
    ...
if (polling_rc_chn_ack(ch, mask, state))
    die(...);
```

Remove the `ret` local variable.