Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu.
Hello Christian Walter, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85845?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins)
Change subject: soc/intel/xeon_sp: Add Xeon ICX-SP support ......................................................................
soc/intel/xeon_sp: Add Xeon ICX-SP support
Add support for the 1st Gen 10nm Xeon-SP CPUs. Supported and tested are dual socket systems with a LBG PCH.
The WhitleyFSP, that is being used here, never has been validated in API mode and has several flaws: - CPU PCIe ports MUST be disabled - QPI links MUST run at degraded speeds
Currently uses the SPR ACPI code.
TEST: Boots to Linux userspace. No errors in coreboot or dmesg visible. TODO: Merge with SPR code base.
Change-Id: I7bb74c0db2c91c87bf623c079f89fd139780160b Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/include/cpu/intel/cpu_ids.h M src/soc/intel/xeon_sp/Makefile.mk A src/soc/intel/xeon_sp/icx/Kconfig A src/soc/intel/xeon_sp/icx/Makefile.mk A src/soc/intel/xeon_sp/icx/chip.c A src/soc/intel/xeon_sp/icx/chip.h A src/soc/intel/xeon_sp/icx/chipset.cb A src/soc/intel/xeon_sp/icx/cpu.c A src/soc/intel/xeon_sp/icx/hob_display.c A src/soc/intel/xeon_sp/icx/include/soc/pci_devs.h A src/soc/intel/xeon_sp/icx/include/soc/soc_msr.h A src/soc/intel/xeon_sp/icx/include/soc/soc_util.h A src/soc/intel/xeon_sp/icx/ramstage.c A src/soc/intel/xeon_sp/icx/reset.c A src/soc/intel/xeon_sp/icx/romstage.c A src/soc/intel/xeon_sp/icx/soc_acpi.c A src/soc/intel/xeon_sp/icx/soc_util.c A src/soc/intel/xeon_sp/icx/upd_display.c 18 files changed, 1,457 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/85845/2