Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35072 )
Change subject: soc/intel/skl/acpi: add description for missing PCIe ports ......................................................................
soc/intel/skl/acpi: add description for missing PCIe ports
According to the documentation, Sunrise PCH-H [1,2] and Lewisburg PCH [3] supports up to 16 PCIe ports. However, apci contains a description for only 12 ports. This patch adds ACPI code for missing ports
[1] page 182, Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, December 2018, Document Number: 332690-005EN
[2] page 180, Intel (R) 200 Series and Intel (R) Z370 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, October 2017, Document Number: 335192-003
[3] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US
Change-Id: I954870136e0c8e5ff5d7ff623c7a6432b829abaf Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/acpi/pcie.asl 1 file changed, 72 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35072/1
diff --git a/src/soc/intel/skylake/acpi/pcie.asl b/src/soc/intel/skylake/acpi/pcie.asl index 84cb437..b039f53 100644 --- a/src/soc/intel/skylake/acpi/pcie.asl +++ b/src/soc/intel/skylake/acpi/pcie.asl @@ -69,7 +69,7 @@
Switch (ToInteger (Arg0)) { - Case (Package () { 1, 5, 9 }) { + Case (Package () { 1, 5, 9, 13 }) { If (PICM) { Return (IQAA) } Else { @@ -77,7 +77,7 @@ } }
- Case (Package () { 2, 6, 10 }) { + Case (Package () { 2, 6, 10, 14 }) { If (PICM) { Return (IQBA) } Else { @@ -85,7 +85,7 @@ } }
- Case (Package () { 3, 7, 11 }) { + Case (Package () { 3, 7, 11, 15 }) { If (PICM) { Return (IQCA) } Else { @@ -93,7 +93,7 @@ } }
- Case (Package () { 4, 8, 12 }) { + Case (Package () { 4, 8, 12, 16 }) { If (PICM) { Return (IQDA) } Else { @@ -314,3 +314,71 @@ Return (IRQM (RPPN)) } } + +Device (RP13) +{ + Name (_ADR, 0x001D0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP14) +{ + Name (_ADR, 0x001D0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP15) +{ + Name (_ADR, 0x001D0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP16) +{ + Name (_ADR, 0x001D0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +}
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35072
to look at the new patch set (#2).
Change subject: soc/intel/skl/acpi: add description for missing PCIe ports ......................................................................
soc/intel/skl/acpi: add description for missing PCIe ports
According to the documentation, Sunrise PCH-H [1,2] and Lewisburg PCH [3] supports up to 16 PCIe ports. However, apci contains a description for only 12 ports. This patch adds ACPI code for missing ports
[1] page 182, Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, December 2018, Document Number: 332690-005EN
[2] page 180, Intel (R) 200 Series and Intel (R) Z370 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, October 2017, Document Number: 335192-003
[3] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US
Change-Id: I954870136e0c8e5ff5d7ff623c7a6432b829abaf Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/pcie.asl 2 files changed, 76 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35072/2
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35072
to look at the new patch set (#4).
Change subject: soc/intel/skl/acpi: add description for missing PCIe ports ......................................................................
soc/intel/skl/acpi: add description for missing PCIe ports
According to the documentation, Sunrise PCH-H [1,2] and Lewisburg PCH [3] supports up to 16 PCIe ports. However, apci contains a description for only 12 ports. This patch adds ACPI code for missing ports
[1] page 182, Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, December 2018, Document Number: 332690-005EN
[2] page 180, Intel (R) 200 Series and Intel (R) Z370 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, October 2017, Document Number: 335192-003
[3] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US
Change-Id: I954870136e0c8e5ff5d7ff623c7a6432b829abaf Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/pcie.asl 2 files changed, 76 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35072/4
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35072 )
Change subject: soc/intel/skl/acpi: add description for missing PCIe ports ......................................................................
Patch Set 7: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/35072/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35072/7//COMMIT_MSG@10 PS7, Line 10: apci acpi
Hello Patrick Rudolph, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35072
to look at the new patch set (#8).
Change subject: soc/intel/skl/acpi: add description for missing PCIe ports ......................................................................
soc/intel/skl/acpi: add description for missing PCIe ports
According to the documentation, Sunrise PCH-H [1,2] and Lewisburg PCH [3] supports up to 16 PCIe ports. However, ACPI contains a description for only 12 ports. This patch adds ACPI code for missing ports
[1] page 182, Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, December 2018, Document Number: 332690-005EN
[2] page 180, Intel (R) 200 Series and Intel (R) Z370 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, October 2017, Document Number: 335192-003
[3] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US
Change-Id: I954870136e0c8e5ff5d7ff623c7a6432b829abaf Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/pcie.asl 2 files changed, 76 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35072/8
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35072 )
Change subject: soc/intel/skl/acpi: add description for missing PCIe ports ......................................................................
Patch Set 8:
(1 comment)
Patch Set 7: Code-Review+2
(1 comment)
Thank you! :)
https://review.coreboot.org/c/coreboot/+/35072/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35072/7//COMMIT_MSG@10 PS7, Line 10: apci
acpi
Fixed
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35072 )
Change subject: soc/intel/skl/acpi: add description for missing PCIe ports ......................................................................
Patch Set 8:
Patch Set 7: Code-Review+2
(1 comment)
Please, set Code-Review+2 again
Thanks
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35072 )
Change subject: soc/intel/skl/acpi: add description for missing PCIe ports ......................................................................
Patch Set 8: Code-Review+2
Patch Set 8:
Patch Set 7: Code-Review+2
(1 comment)
Please, set Code-Review+2 again
Thanks
Oops, jumping between so many patches confuses me :D
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35072 )
Change subject: soc/intel/skl/acpi: add description for missing PCIe ports ......................................................................
soc/intel/skl/acpi: add description for missing PCIe ports
According to the documentation, Sunrise PCH-H [1,2] and Lewisburg PCH [3] supports up to 16 PCIe ports. However, ACPI contains a description for only 12 ports. This patch adds ACPI code for missing ports
[1] page 182, Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, December 2018, Document Number: 332690-005EN
[2] page 180, Intel (R) 200 Series and Intel (R) Z370 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, October 2017, Document Number: 335192-003
[3] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US
Change-Id: I954870136e0c8e5ff5d7ff623c7a6432b829abaf Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35072 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/pcie.asl 2 files changed, 76 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index aa51cbe..ccfc7b7 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -805,6 +805,10 @@ case PCH_DEVFN_PCIE10: return "RP10"; case PCH_DEVFN_PCIE11: return "RP11"; case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_PCIE13: return "RP13"; + case PCH_DEVFN_PCIE14: return "RP14"; + case PCH_DEVFN_PCIE15: return "RP15"; + case PCH_DEVFN_PCIE16: return "RP16"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; case PCH_DEVFN_GSPI0: return "SPI0"; diff --git a/src/soc/intel/skylake/acpi/pcie.asl b/src/soc/intel/skylake/acpi/pcie.asl index 84cb437..b039f53 100644 --- a/src/soc/intel/skylake/acpi/pcie.asl +++ b/src/soc/intel/skylake/acpi/pcie.asl @@ -69,7 +69,7 @@
Switch (ToInteger (Arg0)) { - Case (Package () { 1, 5, 9 }) { + Case (Package () { 1, 5, 9, 13 }) { If (PICM) { Return (IQAA) } Else { @@ -77,7 +77,7 @@ } }
- Case (Package () { 2, 6, 10 }) { + Case (Package () { 2, 6, 10, 14 }) { If (PICM) { Return (IQBA) } Else { @@ -85,7 +85,7 @@ } }
- Case (Package () { 3, 7, 11 }) { + Case (Package () { 3, 7, 11, 15 }) { If (PICM) { Return (IQCA) } Else { @@ -93,7 +93,7 @@ } }
- Case (Package () { 4, 8, 12 }) { + Case (Package () { 4, 8, 12, 16 }) { If (PICM) { Return (IQDA) } Else { @@ -314,3 +314,71 @@ Return (IRQM (RPPN)) } } + +Device (RP13) +{ + Name (_ADR, 0x001D0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP14) +{ + Name (_ADR, 0x001D0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP15) +{ + Name (_ADR, 0x001D0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP16) +{ + Name (_ADR, 0x001D0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +}
-
Angel Pons (Code Review) -
Maxim Polyakov (Code Review)
-
Patrick Georgi (Code Review)