[M] Change in coreboot[main]: mb/google/rex/var/kanix: Update CPU power limit

[Kenneth Chan (Code Review)]

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85998?usp=email )

Change subject: mb/google/rex/var/kanix: Update CPU power limit
......................................................................

mb/google/rex/var/kanix: Update CPU power limit

Update PL1/PL2/PL4 settings for kanix thermal design
PL1_min = 12W
PL1_max = 18W
PL2 = 40W
PL4 = 84W

BUG=b:389726952
BRANCH=firmware-rex-15709.B
TEST=build success and thermal team's confirm

Change-Id: Ie5377d92792b20c33c2628009863c11f5d4bc096
Signed-off-by: Kenneth Chan 
---
M src/mainboard/google/rex/variants/kanix/Makefile.mk
M src/mainboard/google/rex/variants/kanix/overridetree.cb
A src/mainboard/google/rex/variants/kanix/ramstage.c
3 files changed, 88 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/85998/1

diff --git a/src/mainboard/google/rex/variants/kanix/Makefile.mk b/src/mainboard/google/rex/variants/kanix/Makefile.mk
index 2638540..03a1836 100644
--- a/src/mainboard/google/rex/variants/kanix/Makefile.mk
+++ b/src/mainboard/google/rex/variants/kanix/Makefile.mk
@@ -4,3 +4,4 @@
 romstage-y += gpio.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb
index 0d76351..a8ca721 100644
--- a/src/mainboard/google/rex/variants/kanix/overridetree.cb
+++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb
@@ -40,6 +40,12 @@

chip soc/intel/meteorlake

+        register "power_limits_config[MTL_P_282_242_CORE]" = "{
+                .tdp_pl1_override = 18,
+                .tdp_pl2_override = 40,
+                .tdp_pl4 = 84,
+        }"
+
    register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C1
    register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB2_C0
    register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"		# Type-A Port A1
@@ -218,15 +224,15 @@
    			## Power Limits Control
    			register "controls.power_limits" = "{
    					.pl1 = {
-							.min_power = 15000,
-							.max_power = 15000,
+							.min_power = 12000,
+							.max_power = 18000,
    						.time_window_min = 28 * MSECS_PER_SEC,
    						.time_window_max = 32 * MSECS_PER_SEC,
    						.granularity = 200,
    					},
    					.pl2 = {
-							.min_power = 57000,
-							.max_power = 57000,
+							.min_power = 40000,
+							.max_power = 40000,
    						.time_window_min = 28 * MSECS_PER_SEC,
    						.time_window_max = 32 * MSECS_PER_SEC,
    						.granularity = 1000,
diff --git a/src/mainboard/google/rex/variants/kanix/ramstage.c b/src/mainboard/google/rex/variants/kanix/ramstage.c
new file mode 100644
index 0000000..87efbca
--- /dev/null
+++ b/src/mainboard/google/rex/variants/kanix/ramstage.c
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <ec/google/chromeec/ec.h>
+
+/*
+ * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
+ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
+ * Following values are for performance config as per document #640982
+ */
+
+const struct cpu_tdp_power_limits variant_perf_efficient_limits[] = {
+	{
+		.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
+		.cpu_tdp = 15,
+		.power_limits_index = MTL_P_282_242_CORE,
+		.pl1_min_power = 12000,
+		.pl1_max_power = 18000,
+		.pl2_min_power = 40000,
+		.pl2_max_power = 40000,
+		.pl4_power = 84000
+	},
+	{
+		.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
+		.cpu_tdp = 15,
+		.power_limits_index = MTL_P_282_242_CORE,
+		.pl1_min_power = 12000,
+		.pl1_max_power = 18000,
+		.pl2_min_power = 40000,
+		.pl2_max_power = 40000,
+		.pl4_power = 84000
+	},
+};
+
+const struct cpu_tdp_power_limits variant_power_efficient_limits[] = {
+	{
+		.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
+		.cpu_tdp = 15,
+                .power_limits_index = MTL_P_282_242_CORE,
+		.pl1_min_power = 12000,
+		.pl1_max_power = 18000,
+		.pl2_min_power = 40000,
+		.pl2_max_power = 40000,
+		.pl4_power = 47000
+	},
+	{
+		.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
+		.cpu_tdp = 15,
+                .power_limits_index = MTL_P_282_242_CORE,
+		.pl1_min_power = 12000,
+		.pl1_max_power = 18000,
+		.pl2_min_power = 40000,
+		.pl2_max_power = 40000,
+		.pl4_power = 47000
+	},
+};
+
+void variant_devtree_update(void)
+{
+	const struct cpu_tdp_power_limits *limits = variant_perf_efficient_limits;
+	size_t limits_size = ARRAY_SIZE(variant_perf_efficient_limits);
+
+	/*
+	 * If battery is not present or battery level is at or below critical threshold
+	 * to boot a platform with the performance efficient configuration, boot with
+	 * the power optimized configuration.
+	 */
+	if (CONFIG(EC_GOOGLE_CHROMEEC)) {
+		if (!google_chromeec_is_battery_present_and_above_critical_threshold()) {
+			limits = variant_power_efficient_limits;
+			limits_size = ARRAY_SIZE(variant_power_efficient_limits);
+		}
+	}
+
+	variant_update_cpu_power_limits(limits, limits_size);
+}