[XS] Change in coreboot[main]: soc/intel/alderlake: Don't load HsPhy on ADL-N

[Brandon Weeks (Code Review)]

Brandon Weeks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86684?usp=email )

Change subject: soc/intel/alderlake: Don't load HsPhy on ADL-N
......................................................................

soc/intel/alderlake: Don't load HsPhy on ADL-N

ADL-N does not support PCIe 5. Slim Bootloader only loads the HsPhy on
ADL-P and ADL-S boards, so this is an attempt to match that behavior.

Change-Id: Iaaae0e4ce44f8c34f0948e8a292863bad317e8be
Signed-off-by: Brandon Weeks 
---
M src/soc/intel/alderlake/Makefile.mk
M src/soc/intel/alderlake/chip.c
2 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/86684/1

diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk
index 55fc83ea..26ada12 100644
--- a/src/soc/intel/alderlake/Makefile.mk
+++ b/src/soc/intel/alderlake/Makefile.mk
@@ -32,7 +32,9 @@
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += graphics.c
+ifeq ($(SOC_INTEL_ALDERLAKE_PCH_N),n)
 ramstage-y += hsphy.c
+endif
 ramstage-y += lockdown.c
 ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index 0256de4..adcaddd 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -199,8 +199,10 @@

void soc_init_pre_device(void *chip_info)
 {
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
    /* HSPHY FW needs to be loaded before FSP silicon init */
    load_and_init_hsphy();
+#endif

/* Perform silicon specific init. */
    fsp_silicon_init();