Change in coreboot[master]: mb/intel/sm: Add Cr50 support

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51086 )

Change subject: mb/intel/sm: Add Cr50 support
......................................................................

mb/intel/sm: Add Cr50 support

Add Cr50 support over GSPI0.

Change-Id: I33f7427d1675190f65acf14679be93546e6db69a
Signed-off-by: Aamir Bohra 
---
M src/mainboard/intel/shadowmountain/Kconfig
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
M src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c
M src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
4 files changed, 19 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/51086/1

diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig
index 1675f03..da824c7 100644
--- a/src/mainboard/intel/shadowmountain/Kconfig
+++ b/src/mainboard/intel/shadowmountain/Kconfig
@@ -20,6 +20,8 @@
    select HAVE_SPD_IN_CBFS
    select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_SPI_TPM_CR50
+	select MAINBOARD_HAS_TPM2
    select PCIEXP_HOTPLUG
    select SOC_INTEL_ALDERLAKE

@@ -68,4 +70,11 @@
    hex
    default 0x1c000000 # 448 MiB

+config DRIVER_TPM_SPI_BUS
+	default 0x1
+
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 3	# GPE0_DW0_3 (GPP_C3)
+
 endif # BOARD_INTEL_SHADOWMOUNTAIN
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index 58b931f..fb5d09e 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -309,7 +309,14 @@
    	device pci 1d.3 off end # RP12
    	device pci 1e.0 on  end # UART0
    	device pci 1e.1 off end # UART1
-		device pci 1e.2 on  end # GSPI0
+		device pci 1e.2 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""google,cr50""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C3_IRQ)"
+				device spi 0 on end
+			end
+		end # GSPI0
    	device pci 1e.3 off end # GSPI1
    	device pci 1f.0 on
    		chip ec/google/chromeec
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c
index 80a4264..db67fa2 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c
@@ -24,7 +24,7 @@
    /* C0 : EN_PP3300_WLAN */
    PAD_CFG_GPO(GPP_C0, 1, DEEP),
    /* C3 : H1_PCH_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_C3, NONE, PLTRST, LEVEL, INVERT),
+	PAD_CFG_GPI_APIC(GPP_C3, UP_20K, PLTRST, LEVEL, INVERT),
    /* D10 : EN_PP3300_WWAN */
    PAD_CFG_GPO(GPP_D10, 1, DEEP),
    /* D15 : MEM_STRAP_3 */
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
index 090715e..7070e75 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
@@ -90,7 +90,7 @@
    /* C2  : SMBALERT# ==> GPP_C2_STRAP */
    PAD_NC(GPP_C2, NONE),
    /* C3 : H1_PCH_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_C3, NONE, PLTRST, LEVEL, INVERT),
+	PAD_CFG_GPI_APIC(GPP_C3, UP_20K, PLTRST, LEVEL, INVERT),
    /* C4 : EN_PP5000_PEN */
    PAD_CFG_GPO(GPP_C4, 1, DEEP),
    /* C5  : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */