[S] Change in coreboot[master]: soc/intel/alderlake: add power limits for Alder Lake-N 7W soc

[Simon Yang (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Vidya Gopalakrishnan, Paul Fagerburg, Simon Yang.

Hello build bot (Jenkins), Tim Wawrzynczak, Vidya Gopalakrishnan, Sumeet R Pawnikar, Paul Fagerburg,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/67374

to look at the new patch set (#3).

Change subject: soc/intel/alderlake: add power limits for Alder Lake-N 7W soc
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soc/intel/alderlake: add power limits for Alder Lake-N 7W soc

Missing power limit setting for Alder-Lake-N 7W soc.
Document reference: 645548 and 646929

BUG=b:245440443
BRANCH=None
TEST=Build FW and test on nivviks board and there is no error
message "unknown SA ID: 0x4617, skipped power limits configuration."

Signed-off-by: Simon Yang 
Change-Id: Iefe17f5b574cc319fe9aad3850401a8aa8e31270
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/chipset.cb
2 files changed, 27 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/67374/3