Change in coreboot[master]: WIP: Add configurable ramstage support for minimal PCI scanning
ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36389 )
Change subject: WIP: Add configurable ramstage support for minimal PCI scanning ......................................................................
WIP: Add configurable ramstage support for minimal PCI scanning
This CL has changes that allow us to enable a configurable ramstage, and one change that allows us to minimize PCI scanning.
We add two new variables to src/Kconfig: CONFIGURABLE_RAMSTAGE is the overall variable controlling other options for minimizing the ramstage.
MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal PCI scanning.
To indicate which devices we must scan, we add a new always_scan struct member to the pci driver. Drivers which must always be scanned can set this to 1.
It is not clear that this approach is close to correct, so comments are welcome.
Change-Id: I5d2432592ef470f877ccb1b5f8a81554a530713e Signed-off-by: Ronald G. Minnich rminnich@gmail.com --- M 3rdparty/fsp M src/Kconfig M src/device/pci_device.c M src/include/device/pci.h 4 files changed, 37 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/36389/1
diff --git a/3rdparty/fsp b/3rdparty/fsp index 5996417..1d2b7e1 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 59964173e18950debcc6b8856c5c928935ce0b4f +Subproject commit 1d2b7e1a94c6a7c25a6fed1ac37caebf500f5f1a diff --git a/src/Kconfig b/src/Kconfig index 4c71f28..81c41b6 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -335,6 +335,19 @@ Skip PCI enumeration logic and only allocate BAR for fixed devices (bootable devices, TPM over GSPI).
+config CONFIGURABLE_RAMSTAGE + bool "Enable a configurable ramstage" + default y if ARCH_X86 + help + A configurable ramstage allows you to select which parts of the ramstage + to run. + +config MINIMAL_PCI_SCANNING + bool "Enable minimal PCI scanning" + depends on CONFIGURABLE_RAMSTAGE + help + If this option is enabled, coreboot will scan only devices + marked as mandatory in devicetree.cb. endmenu
menu "Mainboard" diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 36b7c82..b7a5314 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -926,6 +926,28 @@ { struct pci_driver *driver;
+ /* + * Look through the list of setup drivers and find one for + * this PCI device. + */ + for (driver = &_pci_drivers[0]; driver != &_epci_drivers[0]; driver++) { + if ((driver->vendor == dev->vendor) && + device_id_match(driver, dev->device)) { + printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n", + dev_path(dev), driver->vendor, driver->device, + (driver->ops->scan_bus ? "bus " : "")); + break; + } + } + + if (CONFIG(MINIMAL_PCI_SCANNING) && driver && !driver->always_scan) { + printk(BIOS_INFO, "Minimal PCI config: DISABLE %s [%04x/%04x] %sops\n", + dev_path(dev), driver->vendor, driver->device, + (driver->ops->scan_bus ? "bus " : "")); + dev->enabled = 0; + } + if (!dev->ops && driver) + dev->ops = (struct device_operations *)driver->ops; if (dev->ops) return;
diff --git a/src/include/device/pci.h b/src/include/device/pci.h index f091105..b755f9e 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -39,6 +39,7 @@ unsigned short vendor; unsigned short device; const unsigned short *devices; + unsigned int always_scan : 1; /* scan even if MINIMAL_PCI is set */ };
struct msix_entry {
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36389 )
Change subject: WIP: Add configurable ramstage support for minimal PCI scanning ......................................................................
Patch Set 1:
(7 comments)
https://review.coreboot.org/c/coreboot/+/36389/1/src/device/pci_device.c File src/device/pci_device.c:
https://review.coreboot.org/c/coreboot/+/36389/1/src/device/pci_device.c@949 PS1, Line 949: if (!dev->ops && driver) code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/36389/1/src/device/pci_device.c@949 PS1, Line 949: if (!dev->ops && driver) please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/36389/1/src/device/pci_device.c@949 PS1, Line 949: if (!dev->ops && driver) suspect code indent for conditional statements (8, 10)
https://review.coreboot.org/c/coreboot/+/36389/1/src/device/pci_device.c@950 PS1, Line 950: dev->ops = (struct device_operations *)driver->ops; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/36389/1/src/device/pci_device.c@950 PS1, Line 950: dev->ops = (struct device_operations *)driver->ops; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/36389/1/src/include/device/pci.h File src/include/device/pci.h:
https://review.coreboot.org/c/coreboot/+/36389/1/src/include/device/pci.h@42 PS1, Line 42: unsigned int always_scan : 1; /* scan even if MINIMAL_PCI is set */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/36389/1/src/include/device/pci.h@42 PS1, Line 42: unsigned int always_scan : 1; /* scan even if MINIMAL_PCI is set */ please, no spaces at the start of a line
ron minnich has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/36389 )
Change subject: WIP: Add configurable ramstage support for minimal PCI scanning ......................................................................
WIP: Add configurable ramstage support for minimal PCI scanning
This CL has changes that allow us to enable a configurable ramstage, and one change that allows us to minimize PCI scanning.
We add two new variables to src/Kconfig: CONFIGURABLE_RAMSTAGE is the overall variable controlling other options for minimizing the ramstage.
MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal PCI scanning.
To indicate which devices we must scan, we add a new always_scan struct member to the pci driver. Drivers which must always be scanned can set this to 1.
It is not clear that this approach is close to correct, so comments are welcome.
Change-Id: I5d2432592ef470f877ccb1b5f8a81554a530713e Signed-off-by: Ronald G. Minnich rminnich@gmail.com --- M src/Kconfig M src/device/pci_device.c M src/include/device/pci.h 3 files changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/36389/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36389 )
Change subject: WIP: Add configurable ramstage support for minimal PCI scanning ......................................................................
Patch Set 2:
(7 comments)
https://review.coreboot.org/c/coreboot/+/36389/2/src/device/pci_device.c File src/device/pci_device.c:
https://review.coreboot.org/c/coreboot/+/36389/2/src/device/pci_device.c@949 PS2, Line 949: if (!dev->ops && driver) code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/36389/2/src/device/pci_device.c@949 PS2, Line 949: if (!dev->ops && driver) please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/36389/2/src/device/pci_device.c@949 PS2, Line 949: if (!dev->ops && driver) suspect code indent for conditional statements (8, 10)
https://review.coreboot.org/c/coreboot/+/36389/2/src/device/pci_device.c@950 PS2, Line 950: dev->ops = (struct device_operations *)driver->ops; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/36389/2/src/device/pci_device.c@950 PS2, Line 950: dev->ops = (struct device_operations *)driver->ops; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/36389/2/src/include/device/pci.h File src/include/device/pci.h:
https://review.coreboot.org/c/coreboot/+/36389/2/src/include/device/pci.h@42 PS2, Line 42: unsigned int always_scan : 1; /* scan even if MINIMAL_PCI is set */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/36389/2/src/include/device/pci.h@42 PS2, Line 42: unsigned int always_scan : 1; /* scan even if MINIMAL_PCI is set */ please, no spaces at the start of a line
ron minnich has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36389 )
Change subject: WIP: Add configurable ramstage support for minimal PCI scanning ......................................................................
Abandoned
git mistake on my part
-
build bot (Jenkins) (Code Review) -
ron minnich (Code Review)