Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85691?usp=email )
Change subject: mb/starlabs/*: Configure GPIO UPDs for eSPI ......................................................................
mb/starlabs/*: Configure GPIO UPDs for eSPI
FSP defaults to using pins that are used for LPC; given that coreboot and these boards only supports eSPI, set these pins accordingly.
If this is not done, FSP will assert and not boot.
Change-Id: Ide4d92211fa7ab496c38ce1c4e895337c269d247 Signed-off-by: Sean Rhodes sean@starlabs.systems Reviewed-on: https://review.coreboot.org/c/coreboot/+/85691 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk A src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c M src/mainboard/starlabs/starbook/variants/adl/ramstage.c M src/mainboard/starlabs/starbook/variants/rpl/ramstage.c M src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c M src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk A src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c 7 files changed, 53 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk b/src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk index 2a505c3..9abc069 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk @@ -7,3 +7,4 @@ ramstage-y += devtree.c ramstage-y += gpio.c ramstage-y += hda_verb.c +ramstage-y += ramstage.c diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c new file mode 100644 index 0000000..80f186e --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *supd) +{ + /* + * FSP defaults to pins that are used for LPC; given that + * coreboot only supports eSPI, set these pins accordingly. + */ + supd->CnviRfResetPinMux = 0x194ce404; // GPP_F4 + supd->CnviClkreqPinMux = 0x294ce605; // GPP_F5 + supd->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13 +} diff --git a/src/mainboard/starlabs/starbook/variants/adl/ramstage.c b/src/mainboard/starlabs/starbook/variants/adl/ramstage.c index a2c3926..9e678de 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/ramstage.c +++ b/src/mainboard/starlabs/starbook/variants/adl/ramstage.c @@ -3,10 +3,17 @@ #include <option.h> #include <soc/ramstage.h>
- void mainboard_silicon_init_params(FSP_S_CONFIG *supd) { /* + * FSP defaults to pins that are used for LPC; given that + * coreboot only supports eSPI, set these pins accordingly. + */ + supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 + supd->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13 + + /* * Enable Hot Plug on RP5 to slow down coreboot so that * third-party drives are detected. */ diff --git a/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c b/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c index bd3d7ed..f62c069 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c @@ -3,9 +3,15 @@ #include <option.h> #include <soc/ramstage.h>
- void mainboard_silicon_init_params(FSP_S_CONFIG *supd) { + /* + * FSP defaults to pins that are used for LPC; given that + * coreboot only supports eSPI, set these pins accordingly. + */ + supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 + if (get_uint_option("thunderbolt", 1) == 0) supd->UsbTcPortEn = 0; } diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c index bd3d7ed..f62c069 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c +++ b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c @@ -3,9 +3,15 @@ #include <option.h> #include <soc/ramstage.h>
- void mainboard_silicon_init_params(FSP_S_CONFIG *supd) { + /* + * FSP defaults to pins that are used for LPC; given that + * coreboot only supports eSPI, set these pins accordingly. + */ + supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 + if (get_uint_option("thunderbolt", 1) == 0) supd->UsbTcPortEn = 0; } diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk b/src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk index 2a505c3..9abc069 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk @@ -7,3 +7,4 @@ ramstage-y += devtree.c ramstage-y += gpio.c ramstage-y += hda_verb.c +ramstage-y += ramstage.c diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c new file mode 100644 index 0000000..c6c16c0 --- /dev/null +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *supd) +{ + /* + * FSP defaults to pins that are used for LPC; given that + * coreboot only supports eSPI, set these pins accordingly. + */ + supd->CnviRfResetPinMux = 0x194ce404; // GPP_F4 + supd->CnviClkreqPinMux = 0x294ce605; // GPP_F5 + supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 +}
-
Sean Rhodes (Code Review)