Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55922 )
Change subject: mb/google/hatch/scout: update gpios and device tree ......................................................................
mb/google/hatch/scout: update gpios and device tree
Scout-specific changes to puff reference following bring-up - copy baseline changes from genesis - update GPIOs - update PCIe ports for TPUs - remove LSPCON - enable eMMC - disable touch I2C - enable uart
BUG=b:187078663 TEST=boot scout BRANCH=none
Signed-off-by: Jeff Chase jnchase@google.com Change-Id: Ic3cb9cf515ab7a4a0ebbee249644dd3f133d8735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55922 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/variants/scout/gpio.c M src/mainboard/google/hatch/variants/scout/include/variant/gpio.h M src/mainboard/google/hatch/variants/scout/overridetree.cb 3 files changed, 144 insertions(+), 54 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/scout/gpio.c b/src/mainboard/google/hatch/variants/scout/gpio.c index 5a911fc..c916d55 100644 --- a/src/mainboard/google/hatch/variants/scout/gpio.c +++ b/src/mainboard/google/hatch/variants/scout/gpio.c @@ -9,33 +9,83 @@ PAD_CFG_GPI(GPP_A16, NONE, DEEP), /* A18 : LAN_PE_ISOLATE_ODL */ PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A19 : Not connected */ + PAD_NC(GPP_A19, NONE), + /* A20 : Not connected */ + PAD_NC(GPP_A20, NONE), /* A23 : M2_WLAN_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
/* B5 : LAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : M2_SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : M2_TPU0_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : CLK_PCIE_REQ3 (not connected) */ + PAD_NC(GPP_B8, NONE), + /* B9 : M2_TPU1_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : M2_WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
/* C0 : SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* C1 : SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C3 : PCH_MBCLK1_R (i350) */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : PCH_MBDAT1_R (i350) */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* C6: M2_WLAN_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), /* C7 : LAN_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), /* C10 : PCH_PCON_RST_ODL */ PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : PCH_PCON_PDB_ODL */ + /* C11 : PCH_PCON1_PDB_ODL */ PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C12 : PCH_RX_TSUM_UART_TX */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* C13 : PCH_RX_TSUM_UART_RX */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* C15 : WLAN_OFF_L */ PAD_CFG_GPO(GPP_C15, 1, DEEP),
- /* E2 : EN_PP_MST_OD */ - PAD_CFG_GPO(GPP_E2, 1, DEEP), - /* E9 : USB_A0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* + * TODO(b/187094460): Re-enable touch screen I2C after resolving USB + * conflict + */ + + /* C18 : PCH_I2C_USI_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19 : PCH_I2C_USI_SDL */ + PAD_NC(GPP_C19, NONE), + + /* D13 : SMBUS_ISP_SCALAR */ + PAD_CFG_GPO(GPP_D13, 0, DEEP), + /* D14 : EC_PCH_INT_L */ + PAD_CFG_GPI_APIC(GPP_D14, NONE, PLTRST, LEVEL, INVERT), + /* D15 : USI_RST_L */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), + + /* E2 : Not connected */ + PAD_NC(GPP_E2, NONE), + /* E3 : TPU_RST_PIN40 */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E7 : TPU_RST_PIN42 */ + PAD_CFG_GPO(GPP_E7, 1, DEEP), + /* E9 : PU 10K to PP3300_SOC_A */ + PAD_NC(GPP_E9, NONE), /* E10 : USB_A1_OC_ODL */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + /* E15 : PCH_TYPEC_UPFB */ + PAD_CFG_GPI(GPP_E15, NONE, DEEP), + + /* E18 : DDI1_CLK */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + /* E19 : DDI1_DATA */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
/* F11 : EMMC_CMD */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), @@ -66,6 +116,10 @@ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5: PCH_I2C_PCON_SCL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : PCH_I2C_TPU_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : PCH_I2C_TPU_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* H22 : PWM_PP3300_BIOZZER */ PAD_CFG_GPO(GPP_H22, 0, DEEP), }; diff --git a/src/mainboard/google/hatch/variants/scout/include/variant/gpio.h b/src/mainboard/google/hatch/variants/scout/include/variant/gpio.h index 79a1410..9dd2434 100644 --- a/src/mainboard/google/hatch/variants/scout/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/scout/include/variant/gpio.h @@ -5,4 +5,7 @@
#include <baseboard/gpio.h>
+#undef EC_SYNC_IRQ +#define EC_SYNC_IRQ GPP_D14_IRQ + #endif diff --git a/src/mainboard/google/hatch/variants/scout/overridetree.cb b/src/mainboard/google/hatch/variants/scout/overridetree.cb index a30dad0..a6e1150 100644 --- a/src/mainboard/google/hatch/variants/scout/overridetree.cb +++ b/src/mainboard/google/hatch/variants/scout/overridetree.cb @@ -13,7 +13,7 @@ [PchSerialIoIndexSPI1] = PchSerialIoPci, [PchSerialIoIndexSPI2] = PchSerialIoDisabled, [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoPci, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }"
@@ -182,16 +182,49 @@ }, }"
- # PCIe port 7 for LAN + # PCIe root port 7 for LAN register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" - # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0"
+ # PCIe root port 8 for WLAN + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + # Uses CLK SRC 3 + register "PcieClkSrcUsage[3]" = "7" + register "PcieClkSrcClkReq[3]" = "3" + + # PCIe root port 9 for SSD (PCIe Lanes 9-12) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + # RP 9 uses CLK SRC 1 + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcClkReq[1]" = "1" + + # PCIe root port 10-12 disabled + register "PcieRpEnable[9]" = "0" + register "PcieRpEnable[10]" = "0" + register "PcieRpEnable[11]" = "0" + + # PCIe root port 13 TPU0 + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + # RP 13 uses CLK SRC 2 + register "PcieClkSrcUsage[2]" = "12" + register "PcieClkSrcClkReq[2]" = "2" + + # PCIe root port 14 TPU1 + register "PcieRpEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "1" + # RP 14 uses CLK SRC 4 + register "PcieClkSrcUsage[4]" = "13" + register "PcieClkSrcClkReq[4]" = "4" + + register "PcieRpEnable[14]" = "0" + register "PcieRpEnable[15]" = "0" + # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B"
@@ -205,38 +238,35 @@ chip drivers/intel/dptf ## Active Policy register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(90, 85), - TEMP_PCT(85, 75), - TEMP_PCT(80, 65), - TEMP_PCT(75, 55), - TEMP_PCT(70, 45),}}" + .thresholds={TEMP_PCT(94, 0),}}" register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(50, 85), - TEMP_PCT(47, 75), - TEMP_PCT(45, 65), - TEMP_PCT(42, 55), - TEMP_PCT(39, 45),}}" + .thresholds={TEMP_PCT(72, 90), + TEMP_PCT(68, 80), + TEMP_PCT(62, 70), + TEMP_PCT(54, 60), + TEMP_PCT(46, 50), + TEMP_PCT(39, 40),}}"
## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)"
## Critical Policy register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)"
## Power Limits Control # PL1 is fixed at 15W, avg over 28-32s interval - # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + # 51-51W PL2 in 1000mW increments, avg over 28-32s interval register "controls.power_limits.pl1" = "{ .min_power = 15000, .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}" + .granularity = 125,}" register "controls.power_limits.pl2" = "{ - .min_power = 25000, - .max_power = 64000, + .min_power = 51000, + .max_power = 51000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000,}" @@ -333,15 +363,13 @@ device usb 3.3 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 3.4 on end + # USB3 Port 5 is not populated + device usb 3.4 off end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Middle"" + register "desc" = ""USB3 M.2 HDMI-to-USB"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "group" = "ACPI_PLD_GROUP(2, 0)" device usb 3.5 on end end end @@ -351,22 +379,9 @@ # RFU - Reserved for Future Use. end # I2C #0 device pci 15.1 off end # I2C #1 - device pci 15.2 on - chip drivers/i2c/generic - register "hid" = ""1AF80175"" - register "name" = ""PS17"" - register "desc" = ""Parade PS175"" - device i2c 4a on end - end - end # I2C #2, PCON PS175. - device pci 15.3 on - chip drivers/i2c/generic - register "hid" = ""10EC2142"" - register "name" = ""RTD2"" - register "desc" = ""Realtek RTD2142"" - device i2c 4a on end - end - end # I2C #3, Realtek RTD2142. + device pci 15.2 off end # I2C #2, PCON PS175. + device pci 15.3 off end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -381,9 +396,9 @@ device i2c 1a on end end end #I2C #4 - device pci 1a.0 on end # eMMC - device pci 1c.6 on - chip drivers/net + device pci 1a.0 on end # eMMC + device pci 1c.6 on # PCI Root Port 7 (LAN) + chip drivers/net # RTL8111H Ethernet NIC register "customized_leds" = "0x05af" register "wake" = "GPE0_DW1_07" # GPP_C7 register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" @@ -393,8 +408,26 @@ register "device_index" = "0" device pci 00.0 on end end - end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + end + device pci 1c.7 on # PCI Root Port 8 (WLAN) + register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot + end + device pci 1d.0 on # PCI Root Port 9 (SSD) + register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot + end + device pci 1d.1 off end # PCI Root Port 10 (Not connected) + device pci 1d.2 off end # PCI Root Port 11 (Not connected) + device pci 1d.3 off end # PCI Root Port 12 (Not connected) + device pci 1d.4 on # PCI Root Port 13 (TPU0) + register "PcieRpSlotImplemented[12]" = "1" # M.2 Slot + end + device pci 1d.5 on # PCI Root Port 14 (TPU1) + register "PcieRpSlotImplemented[13]" = "1" # M.2 Slot + end + device pci 1d.6 on end # PCI Root Port 15 (non-root) + device pci 1d.7 on end # PCI Root Port 16 (non-root) + device pci 1e.0 on end # UART #0 + device pci 1e.1 on end # UART #1 device pci 1e.3 off end # GSPI #1 end
-
Tim Wawrzynczak (Code Review)