Change in coreboot[master]: soc/sifive/fu540 : test and fix code of fu540 spi

[Xiang Wang (Code Review)]

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35117 )

Change subject: soc/sifive/fu540 : test and fix code of fu540 spi
......................................................................

soc/sifive/fu540 : test and fix code of fu540 spi

I tested the SPI through the SD card and fixed some problems.

Change-Id: I60033a148c21bbd5b4946580f6cab0b439d346c6
Signed-off-by: Xiang Wang 
---
M src/soc/sifive/fu540/spi.c
1 file changed, 27 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35117/1

diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c
index 6bf1700..3580146 100644
--- a/src/soc/sifive/fu540/spi.c
+++ b/src/soc/sifive/fu540/spi.c
@@ -61,6 +61,25 @@
    return (uint8_t) out;
 }

+static int spi_claim_bus_(const struct spi_slave *slave)
+{
+	struct spi_ctrl *spictrl = spictrls[slave->bus];
+	spi_reg_csmode csmode;
+	csmode.raw_bits = 0;
+	csmode.mode = FU540_SPI_CSMODE_HOLD;
+	write32(&spictrl->csmode.raw_bits, csmode.raw_bits);
+	return 0;
+}
+
+static void spi_release_bus_(const struct spi_slave *slave)
+{
+	struct spi_ctrl *spictrl = spictrls[slave->bus];
+	spi_reg_csmode csmode;
+	csmode.raw_bits = 0;
+	csmode.mode = FU540_SPI_CSMODE_OFF;
+	write32(&spictrl->csmode.raw_bits, csmode.raw_bits);
+}
+
 static int spi_xfer_(const struct spi_slave *slave,
    	const void *dout, size_t bytesout,
    	void *din, size_t bytesin)
@@ -126,6 +145,8 @@
    sckmode.pol = FU540_SPI_POL_LEADING;
    write32(&spictrl->sckmode.raw_bits, sckmode.raw_bits);

+	write32(&spictrl->csdef, -1);
+
    csmode.raw_bits = 0;
    csmode.mode = FU540_SPI_CSMODE_AUTO;
    write32(&spictrl->csmode.raw_bits, csmode.raw_bits);
@@ -133,7 +154,7 @@
    fmt.raw_bits = 0;
    fmt.proto = FU540_SPI_PROTO_S;
    fmt.endian = FU540_SPI_ENDIAN_BIG;
-	fmt.dir = 1;
+	fmt.dir = 0;
    fmt.len = 8;
    write32(&spictrl->fmt.raw_bits, fmt.raw_bits);

@@ -143,6 +164,8 @@
 struct spi_ctrlr fu540_spi_ctrlr = {
    .xfer  = spi_xfer_,
    .setup = spi_setup_,
+	.claim_bus = spi_claim_bus_,
+	.release_bus = spi_release_bus_,
 };

const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
@@ -187,6 +210,8 @@
    sckmode.pol = config->pol;
    write32(&spictrl->sckmode.raw_bits, sckmode.raw_bits);

+	write32(&spictrl->csdef, -1);
+
    csmode.raw_bits = 0;
    csmode.mode = FU540_SPI_CSMODE_AUTO;
    write32(&spictrl->csmode.raw_bits, csmode.raw_bits);
@@ -194,7 +219,7 @@
    fmt.raw_bits = 0;
    fmt.proto = config->protocol;
    fmt.endian = config->endianness;
-	fmt.dir = 1;
+	fmt.dir = 0;
    fmt.len = config->bits_per_frame;
    write32(&spictrl->fmt.raw_bits, fmt.raw_bits);

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35117 )

Change subject: soc/sifive/fu540 : test and fix code of fu540 spi
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/35117/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/35117/1//COMMIT_MSG@7 
PS1, Line 7: soc/sifive/fu540 : test and fix code of fu540 spi
Please remove the space before the colon.

https://review.coreboot.org/c/coreboot/+/35117/1//COMMIT_MSG@9 
PS1, Line 9: I tested the SPI through the SD card and fixed some problems.
Please elaborate on the problems.

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Xiang Wang (Code Review)]

Hello Patrick Rudolph, ron minnich, Shawn C, build bot (Jenkins), Philipp Hug,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35117

to look at the new patch set (#2).

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

soc/sifive/fu540: test and fix code of fu540 spi

I tested the SPI through the SD card and fixed some problems. Addied two
functions( claim_bus and release_bus). Setting CS signal is invalid by default.

Change-Id: I60033a148c21bbd5b4946580f6cab0b439d346c6
Signed-off-by: Xiang Wang 
---
M src/soc/sifive/fu540/spi.c
1 file changed, 27 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35117/2

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Xiang Wang (Code Review)]

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35117 )

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/35117/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/35117/1//COMMIT_MSG@7 
PS1, Line 7: soc/sifive/fu540 : test and fix code of fu540 spi
> Please remove the space before the colon.

Done

https://review.coreboot.org/c/coreboot/+/35117/1//COMMIT_MSG@9 
PS1, Line 9: I tested the SPI through the SD card and fixed some problems.
> Please elaborate on the problems.

Done

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Xiang Wang (Code Review)]

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35117 )

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

Patch Set 3:

Have anything update?

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Xiang Wang (Code Review)]

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35117 )

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

Patch Set 3:

Have anything update?

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35117 )

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

Patch Set 3: Code-Review+1

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Xiang Wang (Code Review)]

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35117 )

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

Patch Set 3:

Have anything update?

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35117 )

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

Patch Set 3: -Code-Review

(2 comments)

https://review.coreboot.org/c/coreboot/+/35117/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/35117/3//COMMIT_MSG@10 
PS3, Line 10: ( 
space before, not after

https://review.coreboot.org/c/coreboot/+/35117/3/src/soc/sifive/fu540/spi.c 
File src/soc/sifive/fu540/spi.c:

https://review.coreboot.org/c/coreboot/+/35117/3/src/soc/sifive/fu540/spi.c@... 
PS3, Line 148: -1
The argument is uint32_t

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Xiang Wang (Code Review)]

Hello Patrick Rudolph, ron minnich, Arthur Heymans, Shawn C, build bot (Jenkins), Philipp Hug,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35117

to look at the new patch set (#4).

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

soc/sifive/fu540: test and fix code of fu540 spi

I tested the SPI through the SD card and fixed some problems. Addied two
functions (claim_bus and release_bus). Setting CS signal is invalid by default.

Change-Id: I60033a148c21bbd5b4946580f6cab0b439d346c6
Signed-off-by: Xiang Wang 
---
M src/soc/sifive/fu540/spi.c
1 file changed, 27 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35117/4

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Xiang Wang (Code Review)]

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35117 )

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/35117/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/35117/3//COMMIT_MSG@10 
PS3, Line 10: (
> space before, not after

Done

https://review.coreboot.org/c/coreboot/+/35117/3/src/soc/sifive/fu540/spi.c 
File src/soc/sifive/fu540/spi.c:

https://review.coreboot.org/c/coreboot/+/35117/3/src/soc/sifive/fu540/spi.c@... 
PS3, Line 148: -1
> The argument is uint32_t

Done

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35117 )

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35117/4/src/soc/sifive/fu540/spi.c 
File src/soc/sifive/fu540/spi.c:

https://review.coreboot.org/c/coreboot/+/35117/4/src/soc/sifive/fu540/spi.c@... 
PS4, Line 148: (uint32_t)-1
just use 0xffffffff assuming that is what you want to do?

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Xiang Wang (Code Review)]

Hello Patrick Rudolph, ron minnich, Arthur Heymans, Shawn C, build bot (Jenkins), Philipp Hug,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35117

to look at the new patch set (#5).

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

soc/sifive/fu540: test and fix code of fu540 spi

I tested the SPI through the SD card and fixed some problems. Addied two
functions (claim_bus and release_bus). Setting CS signal is invalid by default.

Change-Id: I60033a148c21bbd5b4946580f6cab0b439d346c6
Signed-off-by: Xiang Wang 
---
M src/soc/sifive/fu540/spi.c
1 file changed, 27 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35117/5

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Xiang Wang (Code Review)]

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35117 )

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35117/4/src/soc/sifive/fu540/spi.c 
File src/soc/sifive/fu540/spi.c:

https://review.coreboot.org/c/coreboot/+/35117/4/src/soc/sifive/fu540/spi.c@... 
PS4, Line 148: (uint32_t)-1
> just use 0xffffffff assuming that is what you want to do?

Done

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35117 )

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

Patch Set 5: Code-Review+2

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35117 )

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

Patch Set 5:

(2 comments)

https://review.coreboot.org/c/coreboot/+/35117/5//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/35117/5//COMMIT_MSG@9 
PS5, Line 9: fixed some problems
What problems? Please update the commit message.

https://review.coreboot.org/c/coreboot/+/35117/5//COMMIT_MSG@9 
PS5, Line 9: Addied
Added

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Xiang Wang (Code Review)]

Hello Patrick Rudolph, ron minnich, Arthur Heymans, Shawn C, build bot (Jenkins), Philipp Hug,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35117

to look at the new patch set (#6).

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

soc/sifive/fu540: test and fix code of fu540 spi

I tested the SPI through the SD card and fixed sd card communication problem.
Added two functions (claim_bus and release_bus). Setting CS signal is invalid by
default.

Change-Id: I60033a148c21bbd5b4946580f6cab0b439d346c6
Signed-off-by: Xiang Wang 
---
M src/soc/sifive/fu540/spi.c
1 file changed, 27 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35117/6

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Xiang Wang (Code Review)]

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35117 )

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

Patch Set 6:

Have anything update?

Change in coreboot[master]: soc/sifive/fu540: test and fix code of fu540 spi

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35117 )

Change subject: soc/sifive/fu540: test and fix code of fu540 spi
......................................................................

soc/sifive/fu540: test and fix code of fu540 spi

I tested the SPI through the SD card and fixed sd card communication problem.
Added two functions (claim_bus and release_bus). Setting CS signal is invalid by
default.

Change-Id: I60033a148c21bbd5b4946580f6cab0b439d346c6
Signed-off-by: Xiang Wang 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35117
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/soc/sifive/fu540/spi.c
1 file changed, 27 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved

diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c
index 6bf1700..5e30e77 100644
--- a/src/soc/sifive/fu540/spi.c
+++ b/src/soc/sifive/fu540/spi.c
@@ -61,6 +61,25 @@
    return (uint8_t) out;
 }

+static int spi_claim_bus_(const struct spi_slave *slave)
+{
+	struct spi_ctrl *spictrl = spictrls[slave->bus];
+	spi_reg_csmode csmode;
+	csmode.raw_bits = 0;
+	csmode.mode = FU540_SPI_CSMODE_HOLD;
+	write32(&spictrl->csmode.raw_bits, csmode.raw_bits);
+	return 0;
+}
+
+static void spi_release_bus_(const struct spi_slave *slave)
+{
+	struct spi_ctrl *spictrl = spictrls[slave->bus];
+	spi_reg_csmode csmode;
+	csmode.raw_bits = 0;
+	csmode.mode = FU540_SPI_CSMODE_OFF;
+	write32(&spictrl->csmode.raw_bits, csmode.raw_bits);
+}
+
 static int spi_xfer_(const struct spi_slave *slave,
    	const void *dout, size_t bytesout,
    	void *din, size_t bytesin)
@@ -126,6 +145,8 @@
    sckmode.pol = FU540_SPI_POL_LEADING;
    write32(&spictrl->sckmode.raw_bits, sckmode.raw_bits);

+	write32(&spictrl->csdef, 0xffffffff);
+
    csmode.raw_bits = 0;
    csmode.mode = FU540_SPI_CSMODE_AUTO;
    write32(&spictrl->csmode.raw_bits, csmode.raw_bits);
@@ -133,7 +154,7 @@
    fmt.raw_bits = 0;
    fmt.proto = FU540_SPI_PROTO_S;
    fmt.endian = FU540_SPI_ENDIAN_BIG;
-	fmt.dir = 1;
+	fmt.dir = 0;
    fmt.len = 8;
    write32(&spictrl->fmt.raw_bits, fmt.raw_bits);

@@ -143,6 +164,8 @@
 struct spi_ctrlr fu540_spi_ctrlr = {
    .xfer  = spi_xfer_,
    .setup = spi_setup_,
+	.claim_bus = spi_claim_bus_,
+	.release_bus = spi_release_bus_,
 };

const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
@@ -187,6 +210,8 @@
    sckmode.pol = config->pol;
    write32(&spictrl->sckmode.raw_bits, sckmode.raw_bits);

+	write32(&spictrl->csdef, 0xffffffff);
+
    csmode.raw_bits = 0;
    csmode.mode = FU540_SPI_CSMODE_AUTO;
    write32(&spictrl->csmode.raw_bits, csmode.raw_bits);
@@ -194,7 +219,7 @@
    fmt.raw_bits = 0;
    fmt.proto = config->protocol;
    fmt.endian = config->endianness;
-	fmt.dir = 1;
+	fmt.dir = 0;
    fmt.len = config->bits_per_frame;
    write32(&spictrl->fmt.raw_bits, fmt.raw_bits);