Attention is currently required from: Mario Scheithauer, Paul Menzel, Werner Zeh.
Hello Mario Scheithauer, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79334?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Code-Review+2 by Mario Scheithauer, Verified+1 by build bot (Jenkins)
Change subject: mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1 ......................................................................
mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1
The address space of possible SPD-EEPROMs 0x50..0x53 on the SMBus interface is per default write-protected in FSP. This avoids that an SPD-EEPROM on a DRAM module gets overwritten by the host.
On mc_ehl1, memory-down configuration is used and there is no SPD EEPROM available. Nevertheless, there is a general purpose EEPROM on the same address available which needs to stay writeable.
This patch disables the default-enabled write protect feature for the SPD-EEPROM addresses just for mc_ehl1.
Test=Boot into Linux and make sure a write access into the EEPROM is possible.
Change-Id: I6b0fcdbeb0dbf971cfdceb70d6f4845765a3bdb6 Signed-off-by: Werner Zeh werner.zeh@siemens.com --- M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/79334/2