[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67169 )

Change subject: mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50
......................................................................

mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50

Due to layout restrictions on mc_ehl2, the SD-card interface is limited
to operate in DDR50 mode. The alternative modes SDR104 and SDR50 are not
supported. Limit the capabilities in the SD card controller to DDR50
mode only so that the SD card driver in OS will choose the right mode
for operation even if the attached SD card supports higher modes.

Change-Id: Idc7f1466ec71f4218f6b957cadeeffadd069eb2d
Signed-off-by: Werner Zeh 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67169
Tested-by: build bot (Jenkins) 
Reviewed-by: Mario Scheithauer 
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c
1 file changed, 43 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Mario Scheithauer: Looks good to me, approved

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c
index 36252a7..a798398 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c
@@ -6,8 +6,16 @@
 #include <gpio.h>
 #include <intelblocks/pcr.h>
 #include <soc/gpio.h>
+#include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>

+#define SD_CAP_BYP		0x810
+#define  SD_CAP_BYP_EN		0x5A
+#define SD_CAP_BYP_REG1		0x814
+#define  SD_CAP_BYP_SDR50	(1 << 13)
+#define  SD_CAP_BYP_SDR104	(1 << 14)
+#define  SD_CAP_BYP_DDR50	(1 << 15)
+
 void variant_mainboard_final(void)
 {
    struct device *dev;
@@ -20,6 +28,22 @@
    dev = dev_find_device(PCI_VID_TI, PCI_DID_TI_XIO2001, 0);
    if (dev)
    	pci_write_config8(dev, 0xd8, 0x3e);
+
+	/* Limit SD-Card speed to DDR50 mode to avoid SDR104/SDR50 modes due to
+	   layout limitations. */
+	dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
+	if (dev) {
+		uint32_t reg;
+		struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+		if (!res)
+			return;
+		write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN);
+		reg = read32(res2mmio(res, SD_CAP_BYP_REG1, 0));
+		/* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */
+		reg &= ~(SD_CAP_BYP_SDR104 | SD_CAP_BYP_SDR50);
+		reg |= SD_CAP_BYP_DDR50;
+		write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg);
+	}
 }

static void finalize_boot(void *unused)