Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36641 )
Change subject: arch/x86: Replace some __SMM__ guards ......................................................................
arch/x86: Replace some __SMM__ guards
We generally do not guard source in attempts to reduce the final object sizes, but rely on garbage collection.
Most of the __unused attributes inserted here will be removed when remaining __SIMPLE_DEVICE__ guards can be removed.
Change-Id: I2440931fab4f41d7e8249c082e6c9b5a9cd0ef13 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/google/stout/ec.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/broadwell/xhci.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/common/gpio.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c 14 files changed, 72 insertions(+), 91 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/36641/1
diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 660bb76..3569cae 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -17,6 +17,7 @@ #include <bootmode.h> #include <types.h> #include <console/console.h> +#include <cpu/x86/smm.h> #include <ec/quanta/it8518/ec.h> #include <device/device.h> #include <device/pci.h> @@ -25,11 +26,6 @@ #include <elog.h> #include "ec.h"
-#ifdef __SMM__ -#include <cpu/x86/smm.h> -#endif - -#ifndef __SMM__ void stout_ec_init(void) {
@@ -59,8 +55,6 @@ // TODO: Power Limit Setting }
-#else // SMM - void stout_ec_finalize_smm(void) { u8 ec_reg, critical_shutdown = 0; @@ -120,4 +114,3 @@ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); } } -#endif //__SMM__ diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index b740a03..51174fc 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -16,7 +16,9 @@ #include <stdint.h> #include <arch/acpi.h> #include <arch/io.h> +#include <device/device.h> #include <device/mmio.h> +#include <device/pci.h> #include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> @@ -37,10 +39,7 @@ return pcu_dev; }
-#else /* !__SMM__ */ -#include <device/device.h> -#include <device/pci.h> - +#else static struct device *pcu_dev; static struct device *get_pcu_dev(void) { diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 4bc621b..18cb04d 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -17,7 +17,9 @@ #include <arch/acpi.h> #include <arch/io.h> #include <assert.h> +#include <device/device.h> #include <device/mmio.h> +#include <device/pci.h> #include <device/pci_ops.h> #include <console/console.h> #include <soc/iomap.h> @@ -37,9 +39,7 @@ return pcu_dev; }
-#else /* ENV_SMM */ -#include <device/device.h> -#include <device/pci.h> +#else /* __SIMPLE_DEVICE__ */
static struct device *pcu_dev; static struct device *get_pcu_dev(void) @@ -48,7 +48,7 @@ pcu_dev = pcidev_on_root(PCU_DEV, 0); return pcu_dev; } -#endif /* ENV_SMM */ +#endif /* __SIMPLE_DEVICE__ */
uint16_t get_pmbase(void) { diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 4779987..00b8b8c 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -24,7 +24,7 @@ #include <soc/xhci.h> #include <soc/cpu.h>
-#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ static u8 *usb_xhci_mem_base(pci_devfn_t dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -196,7 +196,7 @@ pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_STATUS_PME); pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_ENABLE_PME); } -#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */
static void xhci_init(struct device *dev) { @@ -235,4 +235,4 @@ .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; -#endif /* !__SMM__ */ +#endif /* !__SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 5e355a1..62a2ed7 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -26,6 +26,8 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> +#include <device/device.h> +#include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_def.h> #include <string.h> @@ -33,11 +35,6 @@ #include <elog.h> #include <halt.h>
-#ifndef __SMM__ -#include <device/device.h> -#include <device/pci.h> -#endif - #include "me.h" #include "pch.h"
@@ -45,9 +42,8 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif
-#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -55,7 +51,6 @@ [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -#endif
/* MMIO base address for MEI interface */ static u32 *mei_base_address; @@ -112,7 +107,7 @@ mei_dump(ptr, dword, offset, "WRITE"); }
-#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); @@ -346,9 +341,8 @@ return 0; }
-#ifdef __SMM__ /* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) +static int __unused mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -370,7 +364,6 @@ printk(BIOS_INFO, "ME: END OF POST message successful\n"); return 0; } -#endif
/* Get ME firmware version */ static int __unused mkhi_get_fw_version(void) @@ -486,7 +479,8 @@ } #endif
-#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ + static void intel_me7_finalize_smm(void) { struct me_hfs hfs; @@ -536,7 +530,8 @@ printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); } } -#else /* !__SMM__ */ + +#else
/* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) @@ -750,4 +745,4 @@ .device = 0x1c3a, };
-#endif /* !__SMM__ */ +#endif /* __SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index c224cb4..3898787 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -24,6 +24,8 @@
#include <arch/acpi.h> #include <device/mmio.h> +#include <device/device.h> +#include <device/pci.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_ids.h> @@ -33,11 +35,6 @@ #include <elog.h> #include <halt.h>
-#ifndef __SMM__ -#include <device/device.h> -#include <device/pci.h> -#endif - #include "me.h" #include "pch.h"
@@ -46,9 +43,8 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif
-#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -57,7 +53,6 @@ [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; static int intel_me_read_mbp(me_bios_payload *mbp_data); -#endif
/* MMIO base address for MEI interface */ static u32 *mei_base_address; @@ -115,7 +110,7 @@ mei_dump(ptr, dword, offset, "WRITE"); }
-#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); @@ -453,10 +448,8 @@ } #endif
-#ifdef __SMM__ - /* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) +static int __unused mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -482,6 +475,8 @@ return 0; }
+#ifdef __SIMPLE_DEVICE__ + void intel_me8_finalize_smm(void) { struct me_hfs hfs; @@ -517,7 +512,7 @@ RCBA32_OR(FD2, PCH_DISABLE_MEI1); }
-#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */
/* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) @@ -754,6 +749,8 @@ .device = 0x1e3a, };
+#endif /* !__SIMPLE_DEVICE__ */ + /****************************************************************************** * */ static u32 me_to_host_words_pending(void) @@ -785,7 +782,7 @@ * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data) +static int __unused intel_me_read_mbp(me_bios_payload *mbp_data) { mbp_header mbp_hdr; mbp_item_header mbp_item_hdr; @@ -909,5 +906,3 @@
return 0; } - -#endif /* !__SMM__ */ diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index de7fc36..3cd39a6 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -17,12 +17,9 @@
#include <console/console.h> #include <delay.h> -#ifdef __SMM__ -#include <device/pci_def.h> -#else /* !__SMM__ */ #include <device/device.h> #include <device/pci.h> -#endif +#include <device/pci_def.h> #include <device/pci_ops.h> #include <string.h>
@@ -145,7 +142,7 @@ return; }
-#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ /* Set bit in function disable register to hide this device */ static void pch_hide_devfn(unsigned int devfn) { diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index 0669b5f..9731d75 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -35,7 +35,7 @@
static u16 get_gpio_base(void) { -#if defined(__SMM__) +#ifdef __SIMPLE_DEVICE__ /* Don't assume GPIO_BASE is still the same */ return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; #else diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index ae13272..ff0410a 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -38,7 +38,7 @@
u16 lpc_get_pmbase(void) { -#if defined(__SMM__) +#ifdef __SIMPLE_DEVICE__ /* Don't assume PMBASE is still the same */ return pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc; #else diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index c944f63..577bc91 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -23,20 +23,17 @@ */
#include <arch/acpi.h> -#include <device/mmio.h> -#include <device/pci_ops.h> #include <console/console.h> -#include <device/pci_ids.h> +#include <device/device.h> +#include <device/mmio.h> +#include <device/pci.h> #include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <string.h> #include <delay.h> #include <elog.h>
-#ifndef __SMM__ -#include <device/device.h> -#include <device/pci.h> -#endif - #include "me.h" #include "pch.h"
@@ -44,9 +41,8 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif
-#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -54,7 +50,6 @@ [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -#endif
/* MMIO base address for MEI interface */ static u32 *mei_base_address; @@ -111,7 +106,7 @@ mei_dump(ptr, dword, offset, "WRITE"); }
-#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ static inline void pci_read_dword_ptr(struct device *dev,void *ptr, int offset) { @@ -131,7 +126,6 @@ mei_write_dword_ptr(csr, MEI_H_CSR); }
-#ifdef __SMM__ static inline void read_me_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_ME_CSR_HA); @@ -348,7 +342,7 @@ }
/* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) +static int __unused mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -371,6 +365,8 @@ return 0; }
+#ifdef __SIMPLE_DEVICE__ + static void intel_me7_finalize_smm(void) { struct me_hfs hfs; @@ -420,7 +416,7 @@ printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); } } -#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */
/* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) @@ -631,4 +627,4 @@ .devices = pci_device_ids };
-#endif /* !__SMM__ */ +#endif /* !__SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 1c45e2d..15b0932 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -45,9 +45,8 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif
-#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -56,7 +55,6 @@ [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev); -#endif
/* MMIO base address for MEI interface */ static u32 *mei_base_address; @@ -557,10 +555,8 @@ } #endif
-#ifdef __SMM__ - /* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) +static int __unused mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -579,6 +575,8 @@ return 0; }
+#ifdef __SIMPLE_DEVICE__ + void intel_me_finalize_smm(void) { struct me_hfs hfs; @@ -619,7 +617,7 @@ RCBA32_OR(FD2, PCH_DISABLE_MEI1); }
-#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */
static inline int mei_sendrecv_icc(struct icc_header *icc, void *req_data, int req_bytes, @@ -903,6 +901,8 @@ .devices= pci_device_ids, };
+#endif /* !__SIMPLE_DEVICE__ */ + /****************************************************************************** * */ static u32 me_to_host_words_pending(void) @@ -940,7 +940,7 @@ * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) +static int __unused intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) { mbp_header mbp_hdr; u32 me2host_pending; @@ -949,7 +949,11 @@ struct mbp_payload *mbp; int i;
+#ifdef __SIMPLE_DEVICE__ + pci_read_dword_ptr(PCI_BDF(dev), &hfs2, PCI_ME_HFS2); +#else pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); +#endif
if (!hfs2.mbp_rdy) { printk(BIOS_ERR, "ME: MBP not ready\n"); @@ -1059,8 +1063,10 @@ return 0;
mbp_failure: +#ifdef __SIMPLE_DEVICE__ + intel_me_mbp_give_up(PCI_BDF(dev)); +#else intel_me_mbp_give_up(dev); +#endif return -1; } - -#endif /* !__SMM__ */ diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index dc7b958..cb50c12 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -90,7 +90,7 @@ return gpiobase; }
-#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__
/* Put device in D3Hot Power State */ static void pch_enable_d3hot(struct device *dev) @@ -330,4 +330,4 @@ .enable_dev = pch_enable, };
-#endif /* __SMM__ */ +#endif /* __SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index bc86053..3e50bee 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -24,7 +24,7 @@ #include <device/pci_ops.h> #include "pch.h"
-#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__
void usb_ehci_disable(pci_devfn_t dev) { @@ -132,7 +132,7 @@ } }
-#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */
static void usb_ehci_clock_gating(struct device *dev) { @@ -202,4 +202,4 @@ .devices = pci_device_ids, };
-#endif /* !__SMM__ */ +#endif /* !__SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 686e06a..4818d62 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -166,7 +166,7 @@ usb_xhci_reset_status_usb3(mem_base, port); }
-#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__
/* Handler for XHCI controller on entry to S3/S4/S5 */ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) @@ -251,7 +251,7 @@ usb_xhci_reset_usb3(PCH_XHCI_DEV, 1); }
-#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */
static void usb_xhci_clock_gating(struct device *dev) { @@ -395,4 +395,4 @@ .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; -#endif /* !__SMM__ */ +#endif /* !__SIMPLE_DEVICE__ */
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36641 )
Change subject: arch/x86: Replace some __SMM__ guards ......................................................................
Patch Set 3: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36641 )
Change subject: arch/x86: Replace some __SMM__ guards ......................................................................
arch/x86: Replace some __SMM__ guards
We generally do not guard source in attempts to reduce the final object sizes, but rely on garbage collection.
Most of the __unused attributes inserted here will be removed when remaining __SIMPLE_DEVICE__ guards can be removed.
Change-Id: I2440931fab4f41d7e8249c082e6c9b5a9cd0ef13 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36641 Reviewed-by: Aaron Durbin adurbin@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/stout/ec.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/broadwell/xhci.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/common/gpio.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c 14 files changed, 72 insertions(+), 91 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved
diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 59987a1..0ea32bc 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -17,6 +17,7 @@ #include <bootmode.h> #include <types.h> #include <console/console.h> +#include <cpu/x86/smm.h> #include <ec/quanta/it8518/ec.h> #include <device/device.h> #include <device/pci.h> @@ -25,11 +26,6 @@ #include <elog.h> #include "ec.h"
-#ifdef __SMM__ -#include <cpu/x86/smm.h> -#endif - -#ifndef __SMM__ void stout_ec_init(void) {
@@ -59,8 +55,6 @@ // TODO: Power Limit Setting }
-#else // SMM - void stout_ec_finalize_smm(void) { u8 ec_reg, critical_shutdown = 0; @@ -105,4 +99,3 @@ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); } } -#endif //__SMM__ diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index b740a03..51174fc 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -16,7 +16,9 @@ #include <stdint.h> #include <arch/acpi.h> #include <arch/io.h> +#include <device/device.h> #include <device/mmio.h> +#include <device/pci.h> #include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> @@ -37,10 +39,7 @@ return pcu_dev; }
-#else /* !__SMM__ */ -#include <device/device.h> -#include <device/pci.h> - +#else static struct device *pcu_dev; static struct device *get_pcu_dev(void) { diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 4bc621b..18cb04d 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -17,7 +17,9 @@ #include <arch/acpi.h> #include <arch/io.h> #include <assert.h> +#include <device/device.h> #include <device/mmio.h> +#include <device/pci.h> #include <device/pci_ops.h> #include <console/console.h> #include <soc/iomap.h> @@ -37,9 +39,7 @@ return pcu_dev; }
-#else /* ENV_SMM */ -#include <device/device.h> -#include <device/pci.h> +#else /* __SIMPLE_DEVICE__ */
static struct device *pcu_dev; static struct device *get_pcu_dev(void) @@ -48,7 +48,7 @@ pcu_dev = pcidev_on_root(PCU_DEV, 0); return pcu_dev; } -#endif /* ENV_SMM */ +#endif /* __SIMPLE_DEVICE__ */
uint16_t get_pmbase(void) { diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 4779987..00b8b8c 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -24,7 +24,7 @@ #include <soc/xhci.h> #include <soc/cpu.h>
-#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ static u8 *usb_xhci_mem_base(pci_devfn_t dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -196,7 +196,7 @@ pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_STATUS_PME); pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_ENABLE_PME); } -#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */
static void xhci_init(struct device *dev) { @@ -235,4 +235,4 @@ .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; -#endif /* !__SMM__ */ +#endif /* !__SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 8adb95b..15f99cd 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -26,6 +26,8 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> +#include <device/device.h> +#include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_def.h> #include <string.h> @@ -33,11 +35,6 @@ #include <elog.h> #include <halt.h>
-#ifndef __SMM__ -#include <device/device.h> -#include <device/pci.h> -#endif - #include "me.h" #include "pch.h"
@@ -45,9 +42,8 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif
-#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -55,7 +51,6 @@ [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -#endif
/* MMIO base address for MEI interface */ static u32 *mei_base_address; @@ -112,7 +107,7 @@ mei_dump(ptr, dword, offset, "WRITE"); }
-#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); @@ -346,9 +341,8 @@ return 0; }
-#ifdef __SMM__ /* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) +static int __unused mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -370,7 +364,6 @@ printk(BIOS_INFO, "ME: END OF POST message successful\n"); return 0; } -#endif
/* Get ME firmware version */ static int __unused mkhi_get_fw_version(void) @@ -486,7 +479,8 @@ } #endif
-#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ + static void intel_me7_finalize_smm(void) { struct me_hfs hfs; @@ -536,7 +530,8 @@ printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); } } -#else /* !__SMM__ */ + +#else
/* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) @@ -748,4 +743,4 @@ .device = 0x1c3a, };
-#endif /* !__SMM__ */ +#endif /* __SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 7af9695..f13ced9 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -24,6 +24,8 @@
#include <arch/acpi.h> #include <device/mmio.h> +#include <device/device.h> +#include <device/pci.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_ids.h> @@ -33,11 +35,6 @@ #include <elog.h> #include <halt.h>
-#ifndef __SMM__ -#include <device/device.h> -#include <device/pci.h> -#endif - #include "me.h" #include "pch.h"
@@ -46,9 +43,8 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif
-#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -57,7 +53,6 @@ [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; static int intel_me_read_mbp(me_bios_payload *mbp_data); -#endif
/* MMIO base address for MEI interface */ static u32 *mei_base_address; @@ -115,7 +110,7 @@ mei_dump(ptr, dword, offset, "WRITE"); }
-#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); @@ -453,10 +448,8 @@ } #endif
-#ifdef __SMM__ - /* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) +static int __unused mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -482,6 +475,8 @@ return 0; }
+#ifdef __SIMPLE_DEVICE__ + void intel_me8_finalize_smm(void) { struct me_hfs hfs; @@ -517,7 +512,7 @@ RCBA32_OR(FD2, PCH_DISABLE_MEI1); }
-#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */
/* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) @@ -752,6 +747,8 @@ .device = 0x1e3a, };
+#endif /* !__SIMPLE_DEVICE__ */ + /****************************************************************************** * */ static u32 me_to_host_words_pending(void) @@ -783,7 +780,7 @@ * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data) +static int __unused intel_me_read_mbp(me_bios_payload *mbp_data) { mbp_header mbp_hdr; mbp_item_header mbp_item_hdr; @@ -907,5 +904,3 @@
return 0; } - -#endif /* !__SMM__ */ diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index de7fc36..3cd39a6 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -17,12 +17,9 @@
#include <console/console.h> #include <delay.h> -#ifdef __SMM__ -#include <device/pci_def.h> -#else /* !__SMM__ */ #include <device/device.h> #include <device/pci.h> -#endif +#include <device/pci_def.h> #include <device/pci_ops.h> #include <string.h>
@@ -145,7 +142,7 @@ return; }
-#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ /* Set bit in function disable register to hide this device */ static void pch_hide_devfn(unsigned int devfn) { diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index 0669b5f..9731d75 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -35,7 +35,7 @@
static u16 get_gpio_base(void) { -#if defined(__SMM__) +#ifdef __SIMPLE_DEVICE__ /* Don't assume GPIO_BASE is still the same */ return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; #else diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index ae13272..ff0410a 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -38,7 +38,7 @@
u16 lpc_get_pmbase(void) { -#if defined(__SMM__) +#ifdef __SIMPLE_DEVICE__ /* Don't assume PMBASE is still the same */ return pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc; #else diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 6aa33ca..63dff6a 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -23,20 +23,17 @@ */
#include <arch/acpi.h> -#include <device/mmio.h> -#include <device/pci_ops.h> #include <console/console.h> -#include <device/pci_ids.h> +#include <device/device.h> +#include <device/mmio.h> +#include <device/pci.h> #include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <string.h> #include <delay.h> #include <elog.h>
-#ifndef __SMM__ -#include <device/device.h> -#include <device/pci.h> -#endif - #include "me.h" #include "pch.h"
@@ -44,9 +41,8 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif
-#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -54,7 +50,6 @@ [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -#endif
/* MMIO base address for MEI interface */ static u32 *mei_base_address; @@ -111,7 +106,7 @@ mei_dump(ptr, dword, offset, "WRITE"); }
-#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__ static inline void pci_read_dword_ptr(struct device *dev,void *ptr, int offset) { @@ -131,7 +126,6 @@ mei_write_dword_ptr(csr, MEI_H_CSR); }
-#ifdef __SMM__ static inline void read_me_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_ME_CSR_HA); @@ -348,7 +342,7 @@ }
/* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) +static int __unused mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -371,6 +365,8 @@ return 0; }
+#ifdef __SIMPLE_DEVICE__ + static void intel_me7_finalize_smm(void) { struct me_hfs hfs; @@ -420,7 +416,7 @@ printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); } } -#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */
/* Determine the path that we should take based on ME status */ static me_bios_path intel_me_path(struct device *dev) @@ -629,4 +625,4 @@ .devices = pci_device_ids };
-#endif /* !__SMM__ */ +#endif /* !__SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 429fa42..2df03c9 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -45,9 +45,8 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif
-#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -56,7 +55,6 @@ [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev); -#endif
/* MMIO base address for MEI interface */ static u32 *mei_base_address; @@ -557,10 +555,8 @@ } #endif
-#ifdef __SMM__ - /* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) +static int __unused mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -579,6 +575,8 @@ return 0; }
+#ifdef __SIMPLE_DEVICE__ + void intel_me_finalize_smm(void) { struct me_hfs hfs; @@ -619,7 +617,7 @@ RCBA32_OR(FD2, PCH_DISABLE_MEI1); }
-#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */
static inline int mei_sendrecv_icc(struct icc_header *icc, void *req_data, int req_bytes, @@ -901,6 +899,8 @@ .devices= pci_device_ids, };
+#endif /* !__SIMPLE_DEVICE__ */ + /****************************************************************************** * */ static u32 me_to_host_words_pending(void) @@ -938,7 +938,7 @@ * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) +static int __unused intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) { mbp_header mbp_hdr; u32 me2host_pending; @@ -947,7 +947,11 @@ struct mbp_payload *mbp; int i;
+#ifdef __SIMPLE_DEVICE__ + pci_read_dword_ptr(PCI_BDF(dev), &hfs2, PCI_ME_HFS2); +#else pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); +#endif
if (!hfs2.mbp_rdy) { printk(BIOS_ERR, "ME: MBP not ready\n"); @@ -1057,8 +1061,10 @@ return 0;
mbp_failure: +#ifdef __SIMPLE_DEVICE__ + intel_me_mbp_give_up(PCI_BDF(dev)); +#else intel_me_mbp_give_up(dev); +#endif return -1; } - -#endif /* !__SMM__ */ diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index dc7b958..cb50c12 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -90,7 +90,7 @@ return gpiobase; }
-#ifndef __SMM__ +#ifndef __SIMPLE_DEVICE__
/* Put device in D3Hot Power State */ static void pch_enable_d3hot(struct device *dev) @@ -330,4 +330,4 @@ .enable_dev = pch_enable, };
-#endif /* __SMM__ */ +#endif /* __SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index bc86053..3e50bee 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -24,7 +24,7 @@ #include <device/pci_ops.h> #include "pch.h"
-#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__
void usb_ehci_disable(pci_devfn_t dev) { @@ -132,7 +132,7 @@ } }
-#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */
static void usb_ehci_clock_gating(struct device *dev) { @@ -202,4 +202,4 @@ .devices = pci_device_ids, };
-#endif /* !__SMM__ */ +#endif /* !__SIMPLE_DEVICE__ */ diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 686e06a..4818d62 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -166,7 +166,7 @@ usb_xhci_reset_status_usb3(mem_base, port); }
-#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__
/* Handler for XHCI controller on entry to S3/S4/S5 */ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) @@ -251,7 +251,7 @@ usb_xhci_reset_usb3(PCH_XHCI_DEV, 1); }
-#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */
static void usb_xhci_clock_gating(struct device *dev) { @@ -395,4 +395,4 @@ .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; -#endif /* !__SMM__ */ +#endif /* !__SIMPLE_DEVICE__ */
-
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