[XS] Change in coreboot[main]: soc/intel/alderlake: Don't load HsPhy on ADL-N

[Subrata Banik (Code Review)]

Attention is currently required from: Brandon Weeks, Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro.

Subrata Banik has posted comments on this change by Brandon Weeks. ( https://review.coreboot.org/c/coreboot/+/86684?usp=email )

Change subject: soc/intel/alderlake: Don't load HsPhy on ADL-N
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Patch Set 1:

(1 comment)

File src/soc/intel/alderlake/chip.c:

https://review.coreboot.org/c/coreboot/+/86684/comment/686ae4fc_b780cec5?usp... :
PS1, Line 202: #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
rather than having preprocessor macro check, how about adding a prerequisites check inside load_and_init_hsphy() API for

```
void load_and_init_hsphy(void)
{
    void *hsphy_buf;
    uint8_t hsphy_hash[MAX_HASH_SIZE] = { 0 };
    uint8_t hash_type;
    uint32_t buf_size = HSPHY_PAYLOAD_SIZE;
    pci_devfn_t dev = PCH_DEV_CSE;
    const uint16_t pci_cmd_bme_mem = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
    uint32_t status;

if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)) {
    	printk(BIOS_DEBUG, "HSPHY firmware loading not supported for ADL-N chipset hence, skipping\n");
    	return;
    }

if (!is_devfn_enabled(SA_DEVFN_CPU_PCIE1_0) &&
        !is_devfn_enabled(SA_DEVFN_CPU_PCIE1_1)) {
    	printk(BIOS_DEBUG, "All HSPHY ports disabled, skipping HSPHY loading\n");
    	return;
    }
```