[S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Vikrant L Jadeja.

Karthik Ramasubramanian has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email )

Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training
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Patch Set 21:

(1 comment)

File src/soc/intel/pantherlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/85454/comment/2816c04a_60f07500?usp... :
PS21, Line 387: 	m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
> > Why not try Jérémy's solution for now and use it for as many generations as it works in? "common"  […]

Combining the comment from a similar discussion here: 
https://review.coreboot.org/c/coreboot/+/86452/comment/84dc3ced_2fc8ae13/

I acknowledge there are 2 problems which are coming in the way of common code:
1) UPD name changes during each generation of SoCs
2) New UPD requirement for ESOL in the future.

Those problems can be addressed through one or more of the following:
1) fill_base_esol_fsp_params() that are common/base to all SoCs. We can provide the default implementation in the common code. We can communicate to Intel and ask them to not change the name for these UPDs. If the UPD names change even after that, then we can provide an override to fill_base_esol_fsp_params() in the SoC specific way.
2) Add soc_fill_additional_esol_fsp_params() to support new UPDs. The default implementation does nothing, but the SoC specific UPDs can be filled by the concerned code. Again we can do this when we have to cross that bridge.
3) Versioning scheme as suggested earlier by Julius.

Even if the suggested improvements does not stand the test of time, they will definitely reduce code and logic duplication.