Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59008 )
Change subject: mb/google,samsung: Refactor init_bootmode_straps() ......................................................................
mb/google,samsung: Refactor init_bootmode_straps()
TBD: Add assertions on PCI_DEV and SATA_SP uses.
Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/include/bootmode.h M src/mainboard/google/beltino/Kconfig M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/jecht/Kconfig M src/mainboard/google/jecht/chromeos.c M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/Kconfig M src/mainboard/samsung/stumpy/chromeos.c M src/southbridge/intel/common/Kconfig.common M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/bootmode_stash.c 12 files changed, 52 insertions(+), 111 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/59008/1
diff --git a/src/include/bootmode.h b/src/include/bootmode.h index dc837a7..cdafdf1 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -15,6 +15,9 @@ int get_lid_switch(void); bool mainboard_ec_running_ro(void);
+/* Maintain bootmode across stages. */ +void stash_bootmode(int flag_spi_wp, int flag_rec_mode); + /* Return 1 if display initialization is required. 0 if not. */ int display_init_required(void); int gfx_get_init_done(void); diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 00b33ad..f8db7c3 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -2,6 +2,7 @@ def_bool n select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT + select SOUTHBRIDGE_INTEL_COMMON_BOOTMODE_STASH select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 select SUPERIO_ITE_IT8772F diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 2f47ae2..7c0f213 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -10,9 +10,6 @@ #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h"
-#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -35,34 +32,9 @@ return !get_gpio(GPIO_REC_MODE); }
-int get_write_protect_state(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - -int get_recovery_mode_switch(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - void init_bootmode_straps(void) { - u32 flags = 0; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - - /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (raw_write_protect_state()) - flags |= (1 << FLAG_SPI_WP); - - /* Recovery: GPIO12 = RECOVERY_L, active low */ - if (raw_recovery_mode_switch()) - flags |= (1 << FLAG_REC_MODE); - - /* Developer: Virtual */ - - pci_s_write_config32(dev, SATA_SP, flags); + stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); }
static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 2f54be9..5015816 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -11,6 +11,7 @@ select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 + select SOUTHBRIDGE_INTEL_COMMON_BOOTMODE_STASH
if BOARD_GOOGLE_BASEBOARD_JECHT
diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 91723a0..3d9d33f 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -12,9 +12,6 @@ #include <southbridge/intel/lynxpoint/lp_gpio.h> #include "onboard.h"
-#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -37,34 +34,9 @@ return !get_gpio(GPIO_REC_MODE); }
-int get_write_protect_state(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - -int get_recovery_mode_switch(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - void init_bootmode_straps(void) { - u32 flags = 0; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - - /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (raw_write_protect_state()) - flags |= (1 << FLAG_SPI_WP); - - /* Recovery: GPIO12 = RECOVERY_L, active low */ - if (raw_recovery_mode_switch()) - flags |= (1 << FLAG_REC_MODE); - - /* Developer: Virtual */ - - pci_s_write_config32(dev, SATA_SP, flags); + stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); }
static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index d0574bb..40e11bd 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_PANEL_1_ON_LVDS select SOUTHBRIDGE_INTEL_BD82X6X + select SOUTHBRIDGE_INTEL_COMMON_BOOTMODE_STASH select SUPERIO_SMSC_MEC1308 select HAVE_IFD_BIN select HAVE_ME_BIN diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index eb60c03..0a2a20c 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -11,9 +11,6 @@ #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h"
-#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 - #include "ec.h" #include <ec/smsc/mec1308/ec.h>
@@ -58,31 +55,9 @@ return (gen_pmcon_1 >> 9) & 1; }
-int get_write_protect_state(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - -int get_recovery_mode_switch(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - void init_bootmode_straps(void) { - u32 flags = 0; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - - /* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ - if (raw_write_protect_state()) - flags |= (1 << FLAG_SPI_WP); - /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - if (raw_recovery_mode_switch()) - flags |= (1 << FLAG_REC_MODE); - - pci_s_write_config32(dev, SATA_SP, flags); + stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); }
bool mainboard_ec_running_ro(void) diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 2a706b9..937f3a6 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -12,6 +12,7 @@ select MAINBOARD_HAS_LIBGFXINIT select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X + select SOUTHBRIDGE_INTEL_COMMON_BOOTMODE_STASH select SUPERIO_ITE_IT8772F select HAVE_IFD_BIN select HAVE_ME_BIN diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index ac13bb2..dd5ded2 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -10,9 +10,6 @@ #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h"
-#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -50,32 +47,9 @@ return (gen_pmcon_1 >> 9) & 1; }
-int get_write_protect_state(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - -int get_recovery_mode_switch(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - void init_bootmode_straps(void) { - u32 flags = 0; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - - /* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ - if (raw_write_protect_state()) - flags |= (1 << FLAG_SPI_WP); - - /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - if (raw_recovery_mode_switch()) - flags |= (1 << FLAG_REC_MODE); - - pci_s_write_config32(dev, SATA_SP, flags); + stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); }
static const struct cros_gpio cros_gpios[] = { diff --git a/src/southbridge/intel/common/Kconfig.common b/src/southbridge/intel/common/Kconfig.common index 5d7a4ee..ad39492 100644 --- a/src/southbridge/intel/common/Kconfig.common +++ b/src/southbridge/intel/common/Kconfig.common @@ -67,6 +67,9 @@ config SOUTHBRIDGE_INTEL_COMMON_FINALIZE bool
+config SOUTHBRIDGE_INTEL_COMMON_BOOTMODE_STASH + bool + config SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG def_bool n select HAVE_USBDEBUG diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 1fc3a63..a2978ec 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -48,3 +48,5 @@ smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c
all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC) += rtc.c + +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_BOOTMODE_STASH) += bootmode_stash.c diff --git a/src/southbridge/intel/common/bootmode_stash.c b/src/southbridge/intel/common/bootmode_stash.c new file mode 100644 index 0000000..8c7bde2 --- /dev/null +++ b/src/southbridge/intel/common/bootmode_stash.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <device/pci_ops.h> +#include <device/device.h> +#include <southbridge/intel/bd82x6x/pch.h> + +#define FLAG_SPI_WP 0 +#define FLAG_REC_MODE 1 + +int get_write_protect_state(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; +} + +int get_recovery_mode_switch(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; +} + +void stash_bootmode(int flag_spi_wp, int flag_rec_mode) +{ + u32 flags = 0; + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + + if (flag_spi_wp) + flags |= (1 << FLAG_SPI_WP); + + if (flag_rec_mode) + flags |= (1 << FLAG_REC_MODE); + + pci_s_write_config32(dev, SATA_SP, flags); +} +
-
Kyösti Mälkki (Code Review)