Change in coreboot[master]: soc/intel/tigerlake: Add known CPU Port IDs for GPIO communities

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Patrick Rudolph.
Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52591 )

Change subject: soc/intel/tigerlake: Add known CPU Port IDs for GPIO communities
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soc/intel/tigerlake: Add known CPU Port IDs for GPIO communities

Change-Id: I97c00e1985f319ff1db57314723d8405c2a6cbd2
Signed-off-by: Tim Wawrzynczak 
---
M src/soc/intel/tigerlake/gpio.c
M src/soc/intel/tigerlake/include/soc/pcr_ids.h
2 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/52591/1

diff --git a/src/soc/intel/tigerlake/gpio.c b/src/soc/intel/tigerlake/gpio.c
index 3e45413..e5bbcc4 100644
--- a/src/soc/intel/tigerlake/gpio.c
+++ b/src/soc/intel/tigerlake/gpio.c
@@ -85,6 +85,7 @@
 static const struct pad_community tgl_communities[] = {
    [COMM_0] = { /* GPP B, T, A */
    	.port = PID_GPIOCOM0,
+		.cpu_port = PID_CPU_GPIOCOM0,
    	.first_pad = GPP_B0,
    	.last_pad = GPP_A24,
    	.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
@@ -104,6 +105,7 @@
    },
    [COMM_1] = { /* GPP S, D, H, U, VGPIO */
    	.port = PID_GPIOCOM1,
+		.cpu_port = PID_CPU_GPIOCOM1,
    	.first_pad = GPP_S0,
    	.last_pad = vI2S2_RXD,
    	.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
@@ -142,6 +144,7 @@
    },
    [COMM_4] = { /* GPP F, C, HVCOS, E, JTAG */
    	.port = PID_GPIOCOM4,
+		.cpu_port = PID_CPU_GPIOCOM4,
    	.first_pad = GPP_C0,
    	.last_pad = GPP_DBG_PMODE,
    	.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
@@ -161,6 +164,7 @@
    },
    [COMM_5] = { /* GPP R, SPI */
    	.port = PID_GPIOCOM5,
+		.cpu_port = PID_CPU_GPIOCOM5,
    	.first_pad = GPP_R0,
    	.last_pad = GPP_CLK_LOOPBK,
    	.num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
diff --git a/src/soc/intel/tigerlake/include/soc/pcr_ids.h b/src/soc/intel/tigerlake/include/soc/pcr_ids.h
index 319558a..03d36bf 100644
--- a/src/soc/intel/tigerlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/tigerlake/include/soc/pcr_ids.h
@@ -31,6 +31,12 @@
 #define PID_ESPI	0xc7
 #define PID_SERIALIO	0xcb

+/* CPU Port IDs */
+#define PID_CPU_GPIOCOM0	0xb7
+#define PID_CPU_GPIOCOM1	0xb8
+#define PID_CPU_GPIOCOM4	0xb9
+#define PID_CPU_GPIOCOM5	0xba
+
 /*
  * SPI - DMI Destination ID
  */