Change in coreboot[master]: soc/amd/cezanne/chip: add PCI bus scanning

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50333 )

Change subject: soc/amd/cezanne/chip: add PCI bus scanning
......................................................................

soc/amd/cezanne/chip: add PCI bus scanning

Signed-off-by: Felix Held 
Change-Id: I76b0eb4470ac4a48e1caeaf507b5e6c45bb88119
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50333
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
Reviewed-by: Angel Pons 
---
M src/soc/amd/cezanne/chip.c
1 file changed, 14 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c
index 4a39024..f6cac14 100644
--- a/src/soc/amd/cezanne/chip.c
+++ b/src/soc/amd/cezanne/chip.c
@@ -7,8 +7,22 @@
 #include <types.h>
 #include "chip.h"

+static struct device_operations pci_domain_ops = {
+	.read_resources	= pci_domain_read_resources,
+	.set_resources	= pci_domain_set_resources,
+	.scan_bus	= pci_domain_scan_bus,
+};
+
 static void enable_dev(struct device *dev)
 {
+	/* Set the operations if it is a special bus type */
+	switch (dev->path.type) {
+	case DEVICE_PATH_DOMAIN:
+		dev->ops = &pci_domain_ops;
+		break;
+	default:
+		break;
+	}
 }

static void soc_init(void *chip_info)