[S] Change in coreboot[main]: soc/amd/common/block/lpc: Add ROM2 and ROM3 helper functions

[Patrick Rudolph (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier.

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86583?usp=email )

Change subject: soc/amd/common/block/lpc: Add ROM2 and ROM3 helper functions
......................................................................

soc/amd/common/block/lpc: Add ROM2 and ROM3 helper functions

Add functions to return the position and size of the ROM2 and ROM3
MMIO window that mmap the SPI flash.

TEST: Verified that both functions return sane values.

Change-Id: I10d4f0fe8a38e0ba2784a9839270d5dd3398d47a
Signed-off-by: Patrick Rudolph 
---
M src/soc/amd/common/block/include/amdblocks/lpc.h
M src/soc/amd/common/block/lpc/lpc_util.c
2 files changed, 44 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/86583/1

diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index 558b608..8cbae02 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -103,6 +103,8 @@
 #define   TPM_12_EN			BIT(0)
 #define   TPM_LEGACY_EN			BIT(2)

+#define ROM_ADDRESS_RANGE3_START	0xa8
+
 #define LPC_WIDEIO2_GENERIC_PORT	0x90

#define LPC_ROM_DMA_SRC_ADDR		0xb0
@@ -140,6 +142,9 @@
 void lpc_tpm_decode_spi(void);
 void lpc_enable_rom(void);
 void lpc_enable_spi_prefetch(void);
+uint32_t lpc_get_rom2_region(size_t *bios_size);
+uint64_t lpc_get_rom3_region(size_t *bios_size);
+
 void lpc_disable_spi_rom_sharing(void);

/**
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index 6e4ddcb..7a2459b 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -287,6 +287,45 @@
    pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_END, 0xffff);
 }

+/*
+ * Returns ROM2 MMIO SPI flash region in the lower MMIO space.
+ * The maxium window size is 16 MiB.
+ */
+uint32_t lpc_get_rom2_region(size_t *bios_size)
+{
+	uint16_t start = pci_read_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START);
+	uint16_t end = pci_read_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_END);
+
+	uint32_t rom2_start = start << 16;
+	uint32_t rom2_end = (end << 16) | 0xffff;
+
+	if (rom2_end <= rom2_start) {
+		*bios_size = 0;
+		return 0;
+	}
+
+	*bios_size = rom2_end - rom2_start + 1;
+
+	return rom2_start;
+}
+
+/*
+ * Returns ROM3 MMIO SPI flash region in the high MMIO space.
+ * Default at 0xfd00000000. The maxium window size is 64 MiB.
+ */
+uint64_t lpc_get_rom3_region(size_t *bios_size)
+{
+	uint32_t lower = pci_read_config32(_LPCB_DEV, ROM_ADDRESS_RANGE3_START);
+	uint32_t upper = pci_read_config32(_LPCB_DEV, ROM_ADDRESS_RANGE3_START + 4);
+
+	if (lower || upper)
+		*bios_size = MIN(CONFIG_ROM_SIZE, 64 * MiB);
+	else
+		*bios_size = 0;
+
+	return ((uint64_t)upper << 32) | lower;
+}
+
 void lpc_enable_spi_prefetch(void)
 {
    uint32_t dword;