[L] Change in coreboot[main]: soc/mediatek/mt8196: Add GPUEB support

[Yidi Lin (Code Review)]

Attention is currently required from: Andy Hsu, Hung-Te Lin, Jarried Lin, Yu-Ping Wu.

Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85654?usp=email )

Change subject: soc/mediatek/mt8196: Add GPUEB support
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Patch Set 1:

(18 comments)

File src/soc/mediatek/mt8196/gpueb.c:

https://review.coreboot.org/c/coreboot/+/85654/comment/e33e26d5_90781aec?usp... :
PS1, Line 96: uint32_t
align with first param

https://review.coreboot.org/c/coreboot/+/85654/comment/cdc07421_7c2ee3fa?usp... :
PS1, Line 126: 50
define this value

https://review.coreboot.org/c/coreboot/+/85654/comment/845ff0ed_3ca2e5ca?usp... :
PS1, Line 131: 1000
define this value

https://review.coreboot.org/c/coreboot/+/85654/comment/074a1ca4_1fc758dc?usp... :
PS1, Line 187: 500
define

https://review.coreboot.org/c/coreboot/+/85654/comment/fd02e677_53556142?usp... :
PS1, Line 198: mfg0_rpc_ctrl_shutdown
why do we pass `POWER_ON` to a function named with `_shutdown` ?

https://review.coreboot.org/c/coreboot/+/85654/comment/06faaf1e_c49ac33e?usp... :
PS1, Line 235: tmp_addr
`buf_addr` or just `buf`

https://review.coreboot.org/c/coreboot/+/85654/comment/b5f6e59f_31570c3a?usp... :
PS1, Line 253: need include
no need to

https://review.coreboot.org/c/coreboot/+/85654/comment/7048a7c1_b7386f45?usp... :
PS1, Line 276: int pt_id
`enum pt_fw_idx id`

https://review.coreboot.org/c/coreboot/+/85654/comment/b768ebb6_72b423c8?usp... :
PS1, Line 279: a
align with 2nd `(`

https://review.coreboot.org/c/coreboot/+/85654/comment/08de34b2_dbf8077c?usp... :
PS1, Line 339: .
remove tailing `.`

https://review.coreboot.org/c/coreboot/+/85654/comment/a8057f4b_074d5a8f?usp... :
PS1, Line 369: wait_us(BOOT_TIMEOUT_US, is_boot_up_complete()) == 0
if (!wait_us(BOOT_TIMEOUT_US, is_boot_up_complete()))

File src/soc/mediatek/mt8196/include/soc/gpueb_priv.h:

https://review.coreboot.org/c/coreboot/+/85654/comment/35eec812_7b94236e?usp... :
PS1, Line 21: define MFG_RPC_MFG1_PWR_CON		(GPU_EB_RPC_BASE + 0x0500)	/* 0x4B800500 */
            : #define MFG_RPC_MFG0_PWR_CON		(GPU_EB_RPC_BASE + 0x0504)	/* 0x4B800504 */
just want to confirm that the ordering is correct.

https://review.coreboot.org/c/coreboot/+/85654/comment/008bf51e_bfac3c31?usp... :
PS1, Line 104: 0x00000064
100

https://review.coreboot.org/c/coreboot/+/85654/comment/c8672425_943be18f?usp... :
PS1, Line 117: SW
align with above `SW`

https://review.coreboot.org/c/coreboot/+/85654/comment/0c8117f2_08e694b9?usp... :
PS1, Line 124: PMIC_ACK_SYNC
align

https://review.coreboot.org/c/coreboot/+/85654/comment/393542b3_6737075e?usp... :
PS1, Line 129: MFG_RPC_MFG0_PWR_ACK_2ND_BIT
align

https://review.coreboot.org/c/coreboot/+/85654/comment/1b3c6cff_67ecacce?usp... :
PS1, Line 160: PT_FW_IDX
lower case

File src/soc/mediatek/mt8196/soc.c:

https://review.coreboot.org/c/coreboot/+/85654/comment/cb14dfeb_3a58e663?usp... :
PS1, Line 24: (uint64_t)
no need.