[M] Change in coreboot[main]: arch/riscv: Add SMP support for exception handler

[Maximilian Brune (Code Review)]

Attention is currently required from: Arthur Heymans, Philipp Hug, Xiang W, ron minnich.

Maximilian Brune has uploaded a new patch set (#6) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/68841?usp=email )

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: arch/riscv: Add SMP support for exception handler
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arch/riscv: Add SMP support for exception handler

Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618
Signed-off-by: Xiang Wang 
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M src/arch/riscv/payload.c
M src/arch/riscv/trap_util.S
2 files changed, 116 insertions(+), 111 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/68841/6