Change in coreboot[master]: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT

[Nico Huber (Code Review)]

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51159 )

Change subject: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT
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Patch Set 8:

(1 comment)

File src/soc/intel/common/block/irq/irq.c:

https://review.coreboot.org/c/coreboot/+/51159/comment/9a5dc235_b5a2d92b 
PS7, Line 378: 		/* Map INTA->PIRQ_A, INTB->PIRQ_B, INTC->PIRQ_C, INTD->PIRQ_D */
> Sorry I can make the comment a little more clear, this is how Intel does the mapping for PIC-mode IRQs (IRQ11 for INTA,INTC,INTD, and IRQ10 for INTB).

I'm not convinced. To allow the mapping we provide for the APIC mode,
FSP has to configure PIR registers (ITSS PCR) and then there is no direct
mapping from pins to PIRQs guaranteed. Or do I miss something in that
direction?