Change in coreboot[master]: superiotool: add basic support for SCH5545

[Alexander Couzens (Code Review)]

Alexander Couzens has submitted this change. ( https://review.coreboot.org/c/coreboot/+/20237 )

Change subject: superiotool: add basic support for SCH5545
......................................................................

superiotool: add basic support for SCH5545

Based on the SCH5627 datasheet which is similiar
SCH5545 id 0xc4, SCH5627 id 0xc6.

Change-Id: I81f3f68690d2000a4fa8a1e703c01f54ebbce953
Signed-off-by: Alexander Couzens 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/20237
Reviewed-by: Felix Held 
Tested-by: build bot (Jenkins) 
---
M util/superiotool/smsc.c
1 file changed, 40 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved

diff --git a/util/superiotool/smsc.c b/util/superiotool/smsc.c
index 2fe940c..ab61ba4 100644
--- a/util/superiotool/smsc.c
+++ b/util/superiotool/smsc.c
@@ -972,6 +972,39 @@
    {0x66, "FDC37C666GT", {
    	/* Init: 0x55, 0x55. Exit: 0xaa. Port: 0x3f0. Chiprev: 0x02. */
    	{EOT}}},
+	{0xc4, "SCH5545", {
+		/* based on SCH5627 datasheet */
+		/* Init: 0x55. Exit: 0xaa. */
+		{0x7, "COM1",
+			{0x30, 0xf0, EOT},
+			{0x00, 0x00, EOT}},
+		{0x0c, "LPC Interface",
+			{0x30,
+			/* IRQ config */
+			 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
+			 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
+			/* DMA Channel 0 - 7 */
+			 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
+			 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
+			/* BAR configuration port */
+			 0x60, 0x61, 0x62, 0x63,
+			/* BAR EMI */
+			 0x64, 0x65, 0x66, 0x67,
+			/* BAR UART1 */
+			 0x68, 0x69, 0x6a, 0x6b,
+			/* BAR UART2 */
+			 0x6c, 0x6d, 0x6e, 0x6f,
+			/* BAR Runtime Registers */
+			 0x70, 0x71, 0x72, 0x73,
+			/* BAR 8042 */
+			 0x78, 0x79, 0x7a, 0x7b,
+			/* BAR Floppy Disk Controller */
+			 0x7c, 0x7d, 0x7e, 0x7f,
+			/* BAR Parallel Port */
+			 0x80, 0x81, 0x82, 0x83,
+			EOT},
+			{EOT}},
+		{EOT}}},
    {EOT}
 };

@@ -1043,6 +1076,13 @@
    		else
    			printf("Runtime Register Block not mapped on this Super I/O.\n");
    		break;
+		case 0xc4: /* SMSC5545 */
+			/* choose LPC interface */
+			regwrite(port, LDN_SEL, 0x0c);
+			runtime_base = regval(port, 0x73) << 8;
+			runtime_base |= regval(port, 0x72);
+			dump_io(runtime_base, 0x34);
+			break;
    	default:
    		printf("No extra registers known for this chip.\n");
    	}