Change in coreboot[master]: siemens/mc_apl1: Extend circuit life by clock gating and power gating

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/28268

Change subject: siemens/mc_apl1: Extend circuit life by clock gating and power gating
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siemens/mc_apl1: Extend circuit life by clock gating and power gating

The firmware of devices connected to LPC should deassert the LPC CLKRUN#
signal when there is no bus activity on LPC.

Necessary changes:

- Enable LPC CLKRUN#
- Enable LPC PCE (Power Control Enable)
- Enable LPC CCE (Clock Control Enable)
- Remove I/O decoding range on LPC for COM 3

Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6
Signed-off-by: Mario Scheithauer 
---
M src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
M src/soc/intel/apollolake/include/soc/pcr_ids.h
3 files changed, 18 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/28268/1

diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c
index 10eb3d3..3713683 100644
--- a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c
@@ -84,7 +84,7 @@
    PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),		/* LPC_AD1 */
    PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),		/* LPC_AD2 */
    PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),		/* LPC_AD3 */
-	PAD_CFG_GPI(LPC_CLKRUNB, UP_20K, DEEP),		/* LPC_CLKRUN_N */
+	PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),	/* LPC_CLKRUN_N */
    PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1),	/* LPC_FRAME_N */

/* West Community */
@@ -402,7 +402,7 @@
    PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),		/* LPC_AD1 */
    PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),		/* LPC_AD2 */
    PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),		/* LPC_AD3 */
-	PAD_CFG_GPI(LPC_CLKRUNB, UP_20K, DEEP),		/* LPC_CLKRUN_N */
+	PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),	/* LPC_CLKRUN_N */
    PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1),	/* LPC_FRAME_N */
 };

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
index 540e322..739f6f4 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
@@ -25,6 +25,11 @@
 #include <baseboard/variants.h>
 #include <variant/ptn3460.h>

+/* LPC PCR configuration */
+#define PCR_LPC_PRC            0x341c
+#define PCR_LPC_CCE_EN         0xf
+#define PCR_LPC_PCE_EN         (9 < 8)
+
 void variant_mainboard_final(void)
 {
    int status;
@@ -39,14 +44,21 @@
    else
    	printk(BIOS_INFO, "LCD: Set up PTN was successful.\n");

-	/* Enable additional I/O decoding range on LPC for COM 3 */
-	lpc_open_pmio_window(0x3e8, 8);
-
    /*
     * PIR6 register mapping for PCIe root ports
     * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA#
     */
    pcr_write16(PID_ITSS, 0x314c, 0x0321);
+
+	/* Enable CLKRUN_EN for power gating LPC */
+	lpc_enable_pci_clk_cntl();
+
+	/* Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2
+	 * offset 0x341D bit3 and bit0.
+	 * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2
+	 * offset 0x341C bit [3:0].
+	 */
+	pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
 }

static void wait_for_legacy_dev(void *unused)
diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h
index f816693..878c45b 100644
--- a/src/soc/intel/apollolake/include/soc/pcr_ids.h
+++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h
@@ -31,6 +31,7 @@
 #define PID_GPIO_N	0xC5
 #define PID_ITSS	0xD0
 #define PID_RTC		0xD1
+#define PID_LPC		0xD2

#define PID_AUNIT	0x4d
 #define PID_BUNIT	0x4c