Change in coreboot[master]: soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39152 )
Change subject: soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig ......................................................................
soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig
This change is mainly to control PlatformDebugConsent FSP UPD. PlatformDebugConsent is enabled if SOC_INTEL_<SOC>LAKE_DEBUG_CONSENT != 0. PlatformDebugConsent in FspmUpd.h has the details.
TEST=Able to connect ITP/DCI with target system.
Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 7 files changed, 25 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/39152/1
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 15a5a31..b30b8c6 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -186,6 +186,17 @@ depends on FSP_USE_REPO default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd"
+config SOC_INTEL_ICELAKE_DEBUG_CONSENT + int "Debug Consent for ICL" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + config ENABLE_DISPLAY_OVER_EXT_PCIE_GFX bool "Enable display over external PCIE GFX card" select ALWAYS_LOAD_OPROM diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 0687513..569160f 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -203,15 +203,6 @@
uint8_t PmTimerDisabled;
- /* Desired platform debug type. */ - enum { - DebugConsent_Disabled, - DebugConsent_DCI_DBC, - DebugConsent_DCI, - DebugConsent_USB3_DBC, - DebugConsent_XDP, /* XDP/Mipi60 */ - DebugConsent_USB2_DBC, - } DebugConsent; /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 1f99604..8dd6bfd 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -87,7 +87,7 @@ /* Enable SMBus controller based on config */ m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ICELAKE_DEBUG_CONSENT;
/* Vt-D config */ m_cfg->VtdDisable = 0; diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 79d74b4..c18752f 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -212,4 +212,15 @@ default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE
+config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT + int "Debug Consent for TGL" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + endif diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 5442361..02855b1 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -169,17 +169,6 @@ */ uint32_t PrmrrSize; uint8_t PmTimerDisabled; - /* Desired platform debug type. */ - enum { - DebugConsent_Disabled, - DebugConsent_DCI_DBC, - DebugConsent_DCI, - DebugConsent_USB3_DBC, - DebugConsent_XDP, /* XDP/Mipi60 */ - DebugConsent_USB2_DBC, - DebugConsent_2WIRE_DCI, - DebugConsent_Manual, - } DebugConsent; /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index e88d809..e02eb6a 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -80,7 +80,7 @@ m_cfg->SmbusEnable = config->SmbusEnable;
/* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT;
/* VT-d config */ m_cfg->VtdDisable = 0; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index ed6aa5a..d769615 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -109,7 +109,7 @@ /* Enable SMBus controller based on config */ m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT;
/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39152 )
Change subject: soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39152/1/src/soc/intel/icelake/Kconf... File src/soc/intel/icelake/Kconfig:
https://review.coreboot.org/c/coreboot/+/39152/1/src/soc/intel/icelake/Kconf... PS1, Line 191: make this default to 3 default to 3
https://review.coreboot.org/c/coreboot/+/39152/1/src/soc/intel/icelake/Kconf... PS1, Line 196: is to control controls the
https://review.coreboot.org/c/coreboot/+/39152/1/src/soc/intel/icelake/Kconf... PS1, Line 199: Where are the possible values described?
Hello Patrick Rudolph, Wonkyu Kim, Tim Wawrzynczak, Duncan Laurie, V Sowmya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39152
to look at the new patch set (#2).
Change subject: soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig ......................................................................
soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig
This change is mainly to control PlatformDebugConsent FSP UPD. PlatformDebugConsent is enabled if SOC_INTEL_<SOC>LAKE_DEBUG_CONSENT != 0. PlatformDebugConsent in FspmUpd.h has the details.
TEST=Able to connect ITP/DCI with target system.
Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 7 files changed, 23 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/39152/2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39152 )
Change subject: soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39152/1/src/soc/intel/icelake/Kconf... File src/soc/intel/icelake/Kconfig:
https://review.coreboot.org/c/coreboot/+/39152/1/src/soc/intel/icelake/Kconf... PS1, Line 191: make this default to 3
default to 3
Ack
https://review.coreboot.org/c/coreboot/+/39152/1/src/soc/intel/icelake/Kconf... PS1, Line 196: is to control
controls the
Ack
https://review.coreboot.org/c/coreboot/+/39152/1/src/soc/intel/icelake/Kconf... PS1, Line 199:
Where are the possible values described?
i believe it has answer below as well. FSPMUPD.h
PlatformDebugConsent in FspmUpd.h has the details.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39152 )
Change subject: soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39152/1/src/soc/intel/icelake/Kconf... File src/soc/intel/icelake/Kconfig:
https://review.coreboot.org/c/coreboot/+/39152/1/src/soc/intel/icelake/Kconf... PS1, Line 199:
i believe it has answer below as well. FSPMUPD.h […]
Indeed. It’s pretty inconvenient though. Some people will quit Kconfig, and configure everything again. If there is a way to put it in the description, I’d prefer that despite it means that the comment in the header is duplicated.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39152 )
Change subject: soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39152/1/src/soc/intel/icelake/Kconf... File src/soc/intel/icelake/Kconfig:
https://review.coreboot.org/c/coreboot/+/39152/1/src/soc/intel/icelake/Kconf... PS1, Line 199:
Indeed. It’s pretty inconvenient though. […]
sure
Hello Patrick Rudolph, Wonkyu Kim, Tim Wawrzynczak, Duncan Laurie, V Sowmya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39152
to look at the new patch set (#3).
Change subject: soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig ......................................................................
soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig
This change is mainly to control PlatformDebugConsent FSP UPD. PlatformDebugConsent is enabled if SOC_INTEL_<SOC>LAKE_DEBUG_CONSENT != 0. PlatformDebugConsent in FspmUpd.h has the details.
TEST=Able to connect ITP/DCI with target system.
Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 7 files changed, 34 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/39152/3
V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39152 )
Change subject: soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig ......................................................................
Patch Set 3: Code-Review+2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39152 )
Change subject: soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39152/1/src/soc/intel/icelake/Kconf... File src/soc/intel/icelake/Kconfig:
https://review.coreboot.org/c/coreboot/+/39152/1/src/soc/intel/icelake/Kconf... PS1, Line 199:
sure
Ack
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39152 )
Change subject: soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig ......................................................................
soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig
This change is mainly to control PlatformDebugConsent FSP UPD. PlatformDebugConsent is enabled if SOC_INTEL_<SOC>LAKE_DEBUG_CONSENT != 0. PlatformDebugConsent in FspmUpd.h has the details.
TEST=Able to connect ITP/DCI with target system.
Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39152 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: V Sowmya v.sowmya@intel.com --- M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 7 files changed, 34 insertions(+), 23 deletions(-)
Approvals: build bot (Jenkins): Verified V Sowmya: Looks good to me, approved
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 15a5a31..9e97d2c 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -186,6 +186,22 @@ depends on FSP_USE_REPO default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd"
+config SOC_INTEL_ICELAKE_DEBUG_CONSENT + int "Debug Consent for ICL" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + + Desired platform debug types are + 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), + 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), + 6:Enable (2-wire DCI OOB), 7:Manual + config ENABLE_DISPLAY_OVER_EXT_PCIE_GFX bool "Enable display over external PCIE GFX card" select ALWAYS_LOAD_OPROM diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 0687513..569160f 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -203,15 +203,6 @@
uint8_t PmTimerDisabled;
- /* Desired platform debug type. */ - enum { - DebugConsent_Disabled, - DebugConsent_DCI_DBC, - DebugConsent_DCI, - DebugConsent_USB3_DBC, - DebugConsent_XDP, /* XDP/Mipi60 */ - DebugConsent_USB2_DBC, - } DebugConsent; /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 1f99604..8dd6bfd 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -87,7 +87,7 @@ /* Enable SMBus controller based on config */ m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ICELAKE_DEBUG_CONSENT;
/* Vt-D config */ m_cfg->VtdDisable = 0; diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 79d74b4..8d066f3 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -212,4 +212,19 @@ default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE
+config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT + int "Debug Consent for TGL" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + + Desired platform debug type are + 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), + 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), + 6:Enable (2-wire DCI OOB), 7:Manual endif diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 5442361..02855b1 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -169,17 +169,6 @@ */ uint32_t PrmrrSize; uint8_t PmTimerDisabled; - /* Desired platform debug type. */ - enum { - DebugConsent_Disabled, - DebugConsent_DCI_DBC, - DebugConsent_DCI, - DebugConsent_USB3_DBC, - DebugConsent_XDP, /* XDP/Mipi60 */ - DebugConsent_USB2_DBC, - DebugConsent_2WIRE_DCI, - DebugConsent_Manual, - } DebugConsent; /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index 829e1e3..56124f4 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -80,7 +80,7 @@ m_cfg->SmbusEnable = config->SmbusEnable;
/* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT;
/* VT-d config */ m_cfg->VtdDisable = 0; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index ed6aa5a..d769615 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -109,7 +109,7 @@ /* Enable SMBus controller based on config */ m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ - m_cfg->PlatformDebugConsent = config->DebugConsent; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT;
/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39152 )
Change subject: soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig ......................................................................
Patch Set 4:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/975 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/974 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/973
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Paul Menzel (Code Review)
-
Subrata Banik (Code Review)
-
V Sowmya (Code Review)