Subrata Banik submitted this change.

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Approvals: build bot (Jenkins): Verified V Sowmya: Looks good to me, approved
soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig

This change is mainly to control PlatformDebugConsent FSP UPD.
PlatformDebugConsent is enabled if SOC_INTEL_<SOC>LAKE_DEBUG_CONSENT != 0.
PlatformDebugConsent in FspmUpd.h has the details.

TEST=Able to connect ITP/DCI with target system.

Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
---
M src/soc/intel/icelake/Kconfig
M src/soc/intel/icelake/chip.h
M src/soc/intel/icelake/romstage/fsp_params.c
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
7 files changed, 34 insertions(+), 23 deletions(-)

diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 15a5a31..9e97d2c 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -186,6 +186,22 @@
depends on FSP_USE_REPO
default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd"

+config SOC_INTEL_ICELAKE_DEBUG_CONSENT
+ int "Debug Consent for ICL"
+ # USB DBC is more common for developers so make this default to 3 if
+ # SOC_INTEL_DEBUG_CONSENT=y
+ default 3 if SOC_INTEL_DEBUG_CONSENT
+ default 0
+ help
+ This is to control debug interface on SOC.
+ Setting non-zero value will allow to use DBC or DCI to debug SOC.
+ PlatformDebugConsent in FspmUpd.h has the details.
+
+ Desired platform debug types are
+ 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
+ 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
+ 6:Enable (2-wire DCI OOB), 7:Manual
+
config ENABLE_DISPLAY_OVER_EXT_PCIE_GFX
bool "Enable display over external PCIE GFX card"
select ALWAYS_LOAD_OPROM
diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h
index 0687513..569160f 100644
--- a/src/soc/intel/icelake/chip.h
+++ b/src/soc/intel/icelake/chip.h
@@ -203,15 +203,6 @@

uint8_t PmTimerDisabled;

- /* Desired platform debug type. */
- enum {
- DebugConsent_Disabled,
- DebugConsent_DCI_DBC,
- DebugConsent_DCI,
- DebugConsent_USB3_DBC,
- DebugConsent_XDP, /* XDP/Mipi60 */
- DebugConsent_USB2_DBC,
- } DebugConsent;
/*
* SerialIO device mode selection:
* PchSerialIoDisabled,
diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c
index 1f99604..8dd6bfd 100644
--- a/src/soc/intel/icelake/romstage/fsp_params.c
+++ b/src/soc/intel/icelake/romstage/fsp_params.c
@@ -87,7 +87,7 @@
/* Enable SMBus controller based on config */
m_cfg->SmbusEnable = config->SmbusEnable;
/* Set debug probe type */
- m_cfg->PlatformDebugConsent = config->DebugConsent;
+ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ICELAKE_DEBUG_CONSENT;

/* Vt-D config */
m_cfg->VtdDisable = 0;
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 79d74b4..8d066f3 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -212,4 +212,19 @@
default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE
default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE

+config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT
+ int "Debug Consent for TGL"
+ # USB DBC is more common for developers so make this default to 3 if
+ # SOC_INTEL_DEBUG_CONSENT=y
+ default 3 if SOC_INTEL_DEBUG_CONSENT
+ default 0
+ help
+ This is to control debug interface on SOC.
+ Setting non-zero value will allow to use DBC or DCI to debug SOC.
+ PlatformDebugConsent in FspmUpd.h has the details.
+
+ Desired platform debug type are
+ 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
+ 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
+ 6:Enable (2-wire DCI OOB), 7:Manual
endif
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 5442361..02855b1 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -169,17 +169,6 @@
*/
uint32_t PrmrrSize;
uint8_t PmTimerDisabled;
- /* Desired platform debug type. */
- enum {
- DebugConsent_Disabled,
- DebugConsent_DCI_DBC,
- DebugConsent_DCI,
- DebugConsent_USB3_DBC,
- DebugConsent_XDP, /* XDP/Mipi60 */
- DebugConsent_USB2_DBC,
- DebugConsent_2WIRE_DCI,
- DebugConsent_Manual,
- } DebugConsent;
/*
* SerialIO device mode selection:
* PchSerialIoDisabled,
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
index 829e1e3..56124f4 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
@@ -80,7 +80,7 @@
m_cfg->SmbusEnable = config->SmbusEnable;

/* Set debug probe type */
- m_cfg->PlatformDebugConsent = config->DebugConsent;
+ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT;

/* VT-d config */
m_cfg->VtdDisable = 0;
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index ed6aa5a..d769615 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -109,7 +109,7 @@
/* Enable SMBus controller based on config */
m_cfg->SmbusEnable = config->SmbusEnable;
/* Set debug probe type */
- m_cfg->PlatformDebugConsent = config->DebugConsent;
+ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT;

/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440
Gerrit-Change-Number: 39152
Gerrit-PatchSet: 4
Gerrit-Owner: Subrata Banik <subrata.banik@intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan@google.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-Reviewer: V Sowmya <v.sowmya@intel.com>
Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: merged