Change in coreboot[master]: mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62478 )

Change subject: mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave
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mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave

The Brask DDR4 setting are interleave, due to Moli PCB layer limited and the routing need to smooth, we will use non-interleave for Moli DDR4.

BUG=b:219831754

Signed-off-by: zoey wu 
Change-Id: Iab153f16a3b729e7fa9daaa3dbfbccc70e6d789d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62478
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Zhuohao Lee 
Reviewed-by: Angel Pons 
---
M src/mainboard/google/brya/variants/moli/Makefile.inc
A src/mainboard/google/brya/variants/moli/memory.c
2 files changed, 32 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Zhuohao Lee: Looks good to me, approved
  Angel Pons: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/moli/Makefile.inc b/src/mainboard/google/brya/variants/moli/Makefile.inc
index aa151d6..f5c5897 100644
--- a/src/mainboard/google/brya/variants/moli/Makefile.inc
+++ b/src/mainboard/google/brya/variants/moli/Makefile.inc
@@ -1,6 +1,7 @@
 bootblock-y += gpio.c

romstage-y += gpio.c
+romstage-y += memory.c

ramstage-y += gpio.c
 ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brya/variants/moli/memory.c b/src/mainboard/google/brya/variants/moli/memory.c
new file mode 100644
index 0000000..ad33e9c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/moli/memory.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg ddr4_mem_config = {
+	.type = MEM_TYPE_DDR4,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {50, 20, 25, 25, 25},
+	},
+
+	.ect = 1, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	},
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &ddr4_mem_config;
+}