[S] Change in coreboot[main]: mb/google/brox: Fix CPU crashlog device MMIO memory access

[Angel Pons (Code Review)]

Attention is currently required from: Benjamin Doron, Dinesh Gehlot, Kane Chen, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Paul Menzel, Sowmya Aralguppe, Subrata Banik.

Angel Pons has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/82136?usp=email )

Change subject: mb/google/brox: Fix CPU crashlog device MMIO memory access
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Patch Set 10: -Code-Review

(1 comment)

File src/soc/intel/alderlake/crashlog.c:

https://review.coreboot.org/c/coreboot/+/82136/comment/2d11a895_2d4f6b5d?usp... :
PS10, Line 205: &
> Why bitwise `&`? Did you mean to use logical `&&` operator?

Good point. The code says "if `dw1` and `dw0` don't have any one-bits in common", which is rather odd.

As per the surrounding code, looks like this is a 64-bit register (a memory address?), and a zero address would be invalid. If this is correct, then the check should be:

```suggestion
    if (!dw1 && !dw0) {
```

This would be equivalent, but I feel it's harder to understand so I prefer the former:
```
    if (!(dw1 | dw0)) {
```