Change in coreboot[master]: mb/google/guybrush: Add variant_tpm_gpio_table

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Julius Werner, Rob Barnes, Yu-Ping Wu, Felix Held.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59083 )

Change subject: mb/google/guybrush: Add variant_tpm_gpio_table
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Patch Set 2:

(1 comment)

File src/mainboard/google/guybrush/variants/baseboard/gpio.c:

https://review.coreboot.org/c/coreboot/+/59083/comment/f923cdcd_2276120f 
PS1, Line 260: 	PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
How about configuring both GPIO_3 and GPIO_85 as PAD_INT in verstage. Given that GPIO_3 is supposed to be GPO, I think it should not be receiving any interrupt.

Later when x86 comes out of reset and enters bootblock, GPIOs can be configured correctly. WDYT?

This will simplify the number of tables used. I think Nipperkin BID1 does exactly that - configure both the GPIOs as PAD_INT.