Hello Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39713
to look at the new patch set (#3).
Change subject: soc/intel/xeon_sp: Add basic Cooperlake-SP support ......................................................................
soc/intel/xeon_sp: Add basic Cooperlake-SP support
This adds barebones support.
What works: * Linux kernel boots fine * SIRQ and PCH interupts work fine (only in IOAPIC mode) * PCH devices are usable
What doesn't: * MP init is not there yet, only 1 CPU is up * SMM is not supported * GPIO is not available * All IIO and extended bus numbers enumeration is not yet available * Warm reset flow is untested * MRC cache save/load
TEST=boots into Linux
Signed-off-by: Andrey Petrov anpetrov@fb.com Change-Id: I7c987badc3c53f16ad178369c7e0906d6596e465 --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/cpx/Kconfig A src/soc/intel/xeon_sp/cpx/Makefile.inc A src/soc/intel/xeon_sp/cpx/acpi.c A src/soc/intel/xeon_sp/cpx/acpi/southcluster.asl A src/soc/intel/xeon_sp/cpx/chip.c A src/soc/intel/xeon_sp/cpx/chip.h A src/soc/intel/xeon_sp/cpx/include/soc/cpu.h A src/soc/intel/xeon_sp/cpx/include/soc/gpio.h A src/soc/intel/xeon_sp/cpx/include/soc/irq.h A src/soc/intel/xeon_sp/cpx/include/soc/nvs.h A src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h A src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h A src/soc/intel/xeon_sp/cpx/romstage.c 15 files changed, 895 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/39713/3