New patch to review for coreboot: northbridge/intel/gm45: Use TSC for ramstage timer per default
Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13922
-gerrit
commit 8fb3d9c0493193e5ba5a41d66a95f361fdb47aae Author: Stefan Reinauer stefan.reinauer@coreboot.org Date: Sun Mar 6 01:49:27 2016 -0800
northbridge/intel/gm45: Use TSC for ramstage timer per default
This is a step towards isolating the timer drivers.
Change-Id: I4c9349054be0cf520cd4407be9fb393b664223a4 Signed-off-by: Stefan Reinauer stefan.reinauer@coreboot.org --- src/northbridge/intel/gm45/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 6ee6558..d254b9e 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -26,6 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select VGA select INTEL_EDID select INTEL_GMA_ACPI + select UDELAY_TSC
config CBFS_SIZE hex
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Stefan Reinauer