[XL] Change in coreboot[master]: soc/intel/xeon_sp: Rename nb_acpi.c and add SPR-SP support

[Angel Pons (Code Review)]

Attention is currently required from: Patrick Rudolph, Simon Chou, TimLiu-SMCI, Johnny Lin, Christian Walter, Jian-Ming Wang, Arthur Heymans, Tim Chu, Shelly Chang.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71958 )

Change subject: soc/intel/xeon_sp: Rename nb_acpi.c and add SPR-SP support
......................................................................

Patch Set 8:

(5 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/71958/comment/efb1085b_3b040220 
PS8, Line 9: and rename to uncore_acpi.c
It would be best to rename the file in a separate commit. Currently, the Gerrit diff is meaningless (one file is deleted, a new file is added). The rename can be done before or after adding SPR-SP support.

The same thing was done in CB:51187 and CB:51528 because https://review.coreboot.org/c/coreboot/+/51187/2 (an older patchset of the first change) was unnecessarily hard to review.

File src/soc/intel/xeon_sp/uncore_acpi.c:

https://review.coreboot.org/c/coreboot/+/71958/comment/b176854e_d8c051fc 
PS8, Line 127: #if CONFIG(SOC_INTEL_HAS_CXL)
Instead of using preprocessor, how about placing the CXL specific code in a separate file? It would look like this:

```
    if (CONFIG(SOC_INTEL_HAS_CXL))
    	current = cxl_fill_srat(current);
```

where `cxl_fill_srat()` is a function in a separate file that contains the code in the #if block.

https://review.coreboot.org/c/coreboot/+/71958/comment/215c3710_77a8fb7c 
PS8, Line 205: 8
What is this magic number?

https://review.coreboot.org/c/coreboot/+/71958/comment/12a3a7be_6b9bbfca 
PS8, Line 527: 						if (pciexp_find_extended_cap(dev, PCIE_EXT_CAP_ID_ATS, 0)) {
> Too many leading tabs - consider code refactoring

Please fix. How about moving the code inside the `if (ri->Personality == TYPE_DINO) {` block to a separate function?

Example:

```
    if (ri->Personality == TYPE_DINO)
    	current = xeonsp_create_satc_dino(current, ri);
```

File src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h:

https://review.coreboot.org/c/coreboot/+/71958/comment/a4a7a357_9fa3368e 
PS8, Line 139: #define IioStack0 CSTACK
Not sure if editing FSP UPD headers is a good idea